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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8953.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Global Clock & Reset Controller on MSM89538 9maintainers:10 - Adam Skladowski <a_skl39@protonmail.com>11 - Sireesh Kodali <sireeshkodali@protonmail.com>12 13description: |14 Qualcomm global clock control module provides the clocks, resets and power15 domains on MSM8953.16 17 See also: include/dt-bindings/clock/qcom,gcc-msm8953.h18 19properties:20 compatible:21 const: qcom,gcc-msm895322 23 clocks:24 items:25 - description: Board XO source26 - description: Sleep clock source27 - description: Byte clock from DSI PHY028 - description: Pixel clock from DSI PHY029 - description: Byte clock from DSI PHY130 - description: Pixel clock from DSI PHY131 32 clock-names:33 items:34 - const: xo35 - const: sleep36 - const: dsi0pll37 - const: dsi0pllbyte38 - const: dsi1pll39 - const: dsi1pllbyte40 41required:42 - compatible43 - clocks44 - clock-names45 - '#power-domain-cells'46 47allOf:48 - $ref: qcom,gcc.yaml#49 50unevaluatedProperties: false51 52examples:53 - |54 #include <dt-bindings/clock/qcom,rpmcc.h>55 56 clock-controller@1800000 {57 compatible = "qcom,gcc-msm8953";58 reg = <0x01800000 0x80000>;59 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,60 <&sleep_clk>,61 <&dsi0_phy 1>,62 <&dsi0_phy 0>,63 <&dsi1_phy 1>,64 <&dsi1_phy 0>;65 clock-names = "xo",66 "sleep",67 "dsi0pll",68 "dsi0pllbyte",69 "dsi1pll",70 "dsi1pllbyte";71 #clock-cells = <1>;72 #reset-cells = <1>;73 #power-domain-cells = <1>;74 };75