70 lines · yaml
1# SPDX-License-Identifier: GPL-2.0-only2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8996.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Global Clock & Reset Controller on MSM89968 9maintainers:10 - Stephen Boyd <sboyd@kernel.org>11 - Taniya Das <quic_tdas@quicinc.com>12 13description: |14 Qualcomm global clock control module which provides the clocks, resets and15 power domains on MSM8996.16 17 See also:: include/dt-bindings/clock/qcom,gcc-msm8996.h18 19properties:20 compatible:21 const: qcom,gcc-msm899622 23 clocks:24 minItems: 325 items:26 - description: XO source27 - description: Second XO source28 - description: Sleep clock source29 - description: PCIe 0 PIPE clock (optional)30 - description: PCIe 1 PIPE clock (optional)31 - description: PCIe 2 PIPE clock (optional)32 - description: USB3 PIPE clock (optional)33 - description: UFS RX symbol 0 clock (optional)34 - description: UFS RX symbol 1 clock (optional)35 - description: UFS TX symbol 0 clock (optional)36 37 clock-names:38 minItems: 339 items:40 - const: cxo41 - const: cxo242 - const: sleep_clk43 - const: pcie_0_pipe_clk_src44 - const: pcie_1_pipe_clk_src45 - const: pcie_2_pipe_clk_src46 - const: usb3_phy_pipe_clk_src47 - const: ufs_rx_symbol_0_clk_src48 - const: ufs_rx_symbol_1_clk_src49 - const: ufs_tx_symbol_0_clk_src50 51required:52 - compatible53 - '#power-domain-cells'54 55allOf:56 - $ref: qcom,gcc.yaml#57 58unevaluatedProperties: false59 60examples:61 - |62 clock-controller@300000 {63 compatible = "qcom,gcc-msm8996";64 #clock-cells = <1>;65 #reset-cells = <1>;66 #power-domain-cells = <1>;67 reg = <0x300000 0x90000>;68 };69...70