60 lines · yaml
1# SPDX-License-Identifier: GPL-2.0-only2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/qcom,gcc-qcs404.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Global Clock & Reset Controller on QCS4048 9maintainers:10 - Stephen Boyd <sboyd@kernel.org>11 - Taniya Das <quic_tdas@quicinc.com>12 13description: |14 Qualcomm global clock control module provides the clocks, resets and power15 domains on QCS404.16 17 See also:: include/dt-bindings/clock/qcom,gcc-qcs404.h18 19properties:20 compatible:21 const: qcom,gcc-qcs40422 23 clocks:24 items:25 - description: XO source26 - description: Sleep clock source27 - description: PCIe 0 PIPE clock (optional)28 - description: DSI phy instance 0 dsi clock29 - description: DSI phy instance 0 byte clock30 - description: HDMI phy PLL clock31 32 clock-names:33 items:34 - const: cxo35 - const: sleep_clk36 - const: pcie_0_pipe_clk_src37 - const: dsi0pll38 - const: dsi0pllbyte39 - const: hdmi_pll40 41required:42 - compatible43 - '#power-domain-cells'44 45allOf:46 - $ref: qcom,gcc.yaml#47 48unevaluatedProperties: false49 50examples:51 - |52 clock-controller@1800000 {53 compatible = "qcom,gcc-qcs404";54 reg = <0x01800000 0x80000>;55 #clock-cells = <1>;56 #reset-cells = <1>;57 #power-domain-cells = <1>;58 };59...60