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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/qcom,gcc-sc7280.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Global Clock & Reset Controller on SC72808 9maintainers:10  - Taniya Das <quic_tdas@quicinc.com>11 12description: |13  Qualcomm global clock control module provides the clocks, resets and power14  domains on SC7280.15 16  See also:: include/dt-bindings/clock/qcom,gcc-sc7280.h17 18properties:19  compatible:20    const: qcom,gcc-sc728021 22  clocks:23    items:24      - description: Board XO source25      - description: Board active XO source26      - description: Sleep clock source27      - description: PCIE-0 pipe clock source28      - description: PCIE-1 pipe clock source29      - description: USF phy rx symbol 0 clock source30      - description: USF phy rx symbol 1 clock source31      - description: USF phy tx symbol 0 clock source32      - description: USB30 phy wrapper pipe clock source33 34  clock-names:35    items:36      - const: bi_tcxo37      - const: bi_tcxo_ao38      - const: sleep_clk39      - const: pcie_0_pipe_clk40      - const: pcie_1_pipe_clk41      - const: ufs_phy_rx_symbol_0_clk42      - const: ufs_phy_rx_symbol_1_clk43      - const: ufs_phy_tx_symbol_0_clk44      - const: usb3_phy_wrapper_gcc_usb30_pipe_clk45 46  power-domains:47    items:48      - description: CX domain49 50required:51  - compatible52  - clocks53  - clock-names54  - '#power-domain-cells'55 56allOf:57  - $ref: qcom,gcc.yaml#58 59unevaluatedProperties: false60 61examples:62  - |63    #include <dt-bindings/clock/qcom,rpmh.h>64    #include <dt-bindings/power/qcom-rpmpd.h>65 66    clock-controller@100000 {67      compatible = "qcom,gcc-sc7280";68      reg = <0x00100000 0x1f0000>;69      clocks = <&rpmhcc RPMH_CXO_CLK>,70               <&rpmhcc RPMH_CXO_CLK_A>,71               <&sleep_clk>,72               <&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>,73               <&ufs_phy_rx_symbol_0_clk>, <&ufs_phy_rx_symbol_1_clk>,74               <&ufs_phy_tx_symbol_0_clk>,75               <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;76 77      clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk",78                     "pcie_1_pipe_clk", "ufs_phy_rx_symbol_0_clk",79                     "ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk",80                     "usb3_phy_wrapper_gcc_usb30_pipe_clk";81      power-domains = <&rpmhpd SC7280_CX>;82      #clock-cells = <1>;83      #reset-cells = <1>;84      #power-domain-cells = <1>;85    };86...87