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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/qcom,gcc-sc8280xp.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Global Clock & Reset Controller on SC8280xp8 9maintainers:10 - Bjorn Andersson <bjorn.andersson@linaro.org>11 12description: |13 Qualcomm global clock control module provides the clocks, resets and14 power domains on SC8280xp.15 16 See also:: include/dt-bindings/clock/qcom,gcc-sc8280xp.h17 18properties:19 compatible:20 const: qcom,gcc-sc8280xp21 22 clocks:23 items:24 - description: XO reference clock25 - description: Sleep clock26 - description: UFS memory first RX symbol clock27 - description: UFS memory second RX symbol clock28 - description: UFS memory first TX symbol clock29 - description: UFS card first RX symbol clock30 - description: UFS card second RX symbol clock31 - description: UFS card first TX symbol clock32 - description: Primary USB SuperSpeed pipe clock33 - description: USB4 PHY pipegmux clock source34 - description: USB4 PHY DP gmux clock source35 - description: USB4 PHY sys pipegmux clock source36 - description: USB4 PHY PCIe pipe clock37 - description: USB4 PHY router max pipe clock38 - description: Primary USB4 RX0 clock39 - description: Primary USB4 RX1 clock40 - description: Secondary USB SuperSpeed pipe clock41 - description: Second USB4 PHY pipegmux clock source42 - description: Second USB4 PHY DP gmux clock source43 - description: Second USB4 PHY sys pipegmux clock source44 - description: Second USB4 PHY PCIe pipe clock45 - description: Second USB4 PHY router max pipe clock46 - description: Secondary USB4 RX0 clock47 - description: Secondary USB4 RX1 clock48 - description: Multiport USB first SuperSpeed pipe clock49 - description: Multiport USB second SuperSpeed pipe clock50 - description: PCIe 2a pipe clock51 - description: PCIe 2b pipe clock52 - description: PCIe 3a pipe clock53 - description: PCIe 3b pipe clock54 - description: PCIe 4 pipe clock55 - description: First EMAC controller reference clock56 - description: Second EMAC controller reference clock57 58 power-domains:59 items:60 - description: CX domain61 62 protected-clocks:63 maxItems: 38964 65required:66 - compatible67 - clocks68 - '#power-domain-cells'69 70allOf:71 - $ref: qcom,gcc.yaml#72 73unevaluatedProperties: false74 75examples:76 - |77 #include <dt-bindings/clock/qcom,rpmh.h>78 #include <dt-bindings/power/qcom-rpmpd.h>79 80 clock-controller@100000 {81 compatible = "qcom,gcc-sc8280xp";82 reg = <0x00100000 0x1f0000>;83 clocks = <&rpmhcc RPMH_CXO_CLK>,84 <&sleep_clk>,85 <&ufs_phy_rx_symbol_0_clk>,86 <&ufs_phy_rx_symbol_1_clk>,87 <&ufs_phy_tx_symbol_0_clk>,88 <&ufs_card_rx_symbol_0_clk>,89 <&ufs_card_rx_symbol_1_clk>,90 <&ufs_card_tx_symbol_0_clk>,91 <&usb_0_ssphy>,92 <&gcc_usb4_phy_pipegmux_clk_src>,93 <&gcc_usb4_phy_dp_gmux_clk_src>,94 <&gcc_usb4_phy_sys_pipegmux_clk_src>,95 <&usb4_phy_gcc_usb4_pcie_pipe_clk>,96 <&usb4_phy_gcc_usb4rtr_max_pipe_clk>,97 <&qusb4phy_gcc_usb4_rx0_clk>,98 <&qusb4phy_gcc_usb4_rx1_clk>,99 <&usb_1_ssphy>,100 <&gcc_usb4_1_phy_pipegmux_clk_src>,101 <&gcc_usb4_1_phy_dp_gmux_clk_src>,102 <&gcc_usb4_1_phy_sys_pipegmux_clk_src>,103 <&usb4_1_phy_gcc_usb4_pcie_pipe_clk>,104 <&usb4_1_phy_gcc_usb4rtr_max_pipe_clk>,105 <&qusb4phy_1_gcc_usb4_rx0_clk>,106 <&qusb4phy_1_gcc_usb4_rx1_clk>,107 <&usb_2_ssphy>,108 <&usb_3_ssphy>,109 <&pcie2a_lane>,110 <&pcie2b_lane>,111 <&pcie3a_lane>,112 <&pcie3b_lane>,113 <&pcie4_lane>,114 <&rxc0_ref_clk>,115 <&rxc1_ref_clk>;116 power-domains = <&rpmhpd SC8280XP_CX>;117 118 #clock-cells = <1>;119 #reset-cells = <1>;120 #power-domain-cells = <1>;121 };122...123