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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/qcom,gcc-sdx65.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Global Clock & Reset Controller on SDX658 9maintainers:10 - Vamsi krishna Lanka <quic_vamslank@quicinc.com>11 12description: |13 Qualcomm global clock control module provides the clocks, resets and power14 domains on SDX6515 16 See also:: include/dt-bindings/clock/qcom,gcc-sdx65.h17 18properties:19 compatible:20 const: qcom,gcc-sdx6521 22 clocks:23 items:24 - description: Board XO source25 - description: Board active XO source26 - description: Sleep clock source27 - description: PCIE Pipe clock source28 - description: USB3 phy wrapper pipe clock source29 30 clock-names:31 items:32 - const: bi_tcxo33 - const: bi_tcxo_ao34 - const: sleep_clk35 - const: pcie_pipe_clk36 - const: usb3_phy_wrapper_gcc_usb30_pipe_clk37 38required:39 - compatible40 - clocks41 - clock-names42 - '#power-domain-cells'43 44allOf:45 - $ref: qcom,gcc.yaml#46 47unevaluatedProperties: false48 49examples:50 - |51 #include <dt-bindings/clock/qcom,rpmh.h>52 clock-controller@100000 {53 compatible = "qcom,gcc-sdx65";54 reg = <0x100000 0x1f7400>;55 clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,56 <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;57 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",58 "pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk";59 #clock-cells = <1>;60 #reset-cells = <1>;61 #power-domain-cells = <1>;62 };63...64