73 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8450.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Global Clock & Reset Controller on SM84508 9maintainers:10 - Vinod Koul <vkoul@kernel.org>11 12description: |13 Qualcomm global clock control module provides the clocks, resets and power14 domains on SM845015 16 See also:: include/dt-bindings/clock/qcom,gcc-sm8450.h17 18properties:19 compatible:20 const: qcom,gcc-sm845021 22 clocks:23 items:24 - description: Board XO source25 - description: Sleep clock source26 - description: PCIE 0 Pipe clock source (Optional clock)27 - description: PCIE 1 Pipe clock source (Optional clock)28 - description: PCIE 1 Phy Auxiliary clock source (Optional clock)29 - description: UFS Phy Rx symbol 0 clock source (Optional clock)30 - description: UFS Phy Rx symbol 1 clock source (Optional clock)31 - description: UFS Phy Tx symbol 0 clock source (Optional clock)32 - description: USB3 Phy wrapper pipe clock source (Optional clock)33 minItems: 234 35 clock-names:36 items:37 - const: bi_tcxo38 - const: sleep_clk39 - const: pcie_0_pipe_clk # Optional clock40 - const: pcie_1_pipe_clk # Optional clock41 - const: pcie_1_phy_aux_clk # Optional clock42 - const: ufs_phy_rx_symbol_0_clk # Optional clock43 - const: ufs_phy_rx_symbol_1_clk # Optional clock44 - const: ufs_phy_tx_symbol_0_clk # Optional clock45 - const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock46 minItems: 247 48required:49 - compatible50 - clocks51 - clock-names52 - '#power-domain-cells'53 54allOf:55 - $ref: qcom,gcc.yaml#56 57unevaluatedProperties: false58 59examples:60 - |61 #include <dt-bindings/clock/qcom,rpmh.h>62 clock-controller@100000 {63 compatible = "qcom,gcc-sm8450";64 reg = <0x00100000 0x001f4200>;65 clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;66 clock-names = "bi_tcxo", "sleep_clk";67 #clock-cells = <1>;68 #reset-cells = <1>;69 #power-domain-cells = <1>;70 };71 72...73