65 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/qcom,gpucc-sdm660.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Graphics Clock & Reset Controller on SDM630 and SDM6608 9maintainers:10 - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>11 12description: |13 Qualcomm graphics clock control module provides the clocks, resets and14 power domains on SDM630 and SDM660.15 16 See also dt-bindings/clock/qcom,gpucc-sdm660.h.17 18properties:19 compatible:20 enum:21 - qcom,gpucc-sdm63022 - qcom,gpucc-sdm66023 24 clocks:25 items:26 - description: Board XO source27 - description: GPLL0 main gpu branch28 - description: GPLL0 divider gpu branch29 30 clock-names:31 items:32 - const: xo33 - const: gcc_gpu_gpll0_clk34 - const: gcc_gpu_gpll0_div_clk35 36required:37 - compatible38 - clocks39 - clock-names40 - '#power-domain-cells'41 42allOf:43 - $ref: qcom,gcc.yaml#44 45unevaluatedProperties: false46 47examples:48 - |49 #include <dt-bindings/clock/qcom,gcc-sdm660.h>50 #include <dt-bindings/clock/qcom,rpmcc.h>51 52 clock-controller@5065000 {53 compatible = "qcom,gpucc-sdm660";54 reg = <0x05065000 0x9038>;55 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,56 <&gcc GCC_GPU_GPLL0_CLK>,57 <&gcc GCC_GPU_GPLL0_DIV_CLK>;58 clock-names = "xo", "gcc_gpu_gpll0_clk",59 "gcc_gpu_gpll0_div_clk";60 #clock-cells = <1>;61 #power-domain-cells = <1>;62 #reset-cells = <1>;63 };64...65