94 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Graphics Clock & Reset Controller8 9maintainers:10 - Taniya Das <quic_tdas@quicinc.com>11 12description: |13 Qualcomm graphics clock control module provides the clocks, resets and power14 domains on Qualcomm SoCs.15 16 See also::17 include/dt-bindings/clock/qcom,gpucc-sdm845.h18 include/dt-bindings/clock/qcom,gpucc-sa8775p.h19 include/dt-bindings/clock/qcom,gpucc-sc7180.h20 include/dt-bindings/clock/qcom,gpucc-sc7280.h21 include/dt-bindings/clock/qcom,gpucc-sc8280xp.h22 include/dt-bindings/clock/qcom,gpucc-sm6350.h23 include/dt-bindings/clock/qcom,gpucc-sm8150.h24 include/dt-bindings/clock/qcom,gpucc-sm8250.h25 include/dt-bindings/clock/qcom,gpucc-sm8350.h26 27properties:28 compatible:29 enum:30 - qcom,sdm845-gpucc31 - qcom,sa8775p-gpucc32 - qcom,sc7180-gpucc33 - qcom,sc7280-gpucc34 - qcom,sc8180x-gpucc35 - qcom,sc8280xp-gpucc36 - qcom,sm6350-gpucc37 - qcom,sm8150-gpucc38 - qcom,sm8250-gpucc39 - qcom,sm8350-gpucc40 41 clocks:42 items:43 - description: Board XO source44 - description: GPLL0 main branch source45 - description: GPLL0 div branch source46 47 clock-names:48 items:49 - const: bi_tcxo50 - const: gcc_gpu_gpll0_clk_src51 - const: gcc_gpu_gpll0_div_clk_src52 53 power-domains:54 maxItems: 155 56 vdd-gfx-supply:57 description: Regulator supply for the VDD_GFX pads58 59required:60 - compatible61 - clocks62 - clock-names63 - '#power-domain-cells'64 65# Require that power-domains and vdd-gfx-supply are not both present66not:67 required:68 - power-domains69 - vdd-gfx-supply70 71allOf:72 - $ref: qcom,gcc.yaml#73 74unevaluatedProperties: false75 76examples:77 - |78 #include <dt-bindings/clock/qcom,gcc-sdm845.h>79 #include <dt-bindings/clock/qcom,rpmh.h>80 clock-controller@5090000 {81 compatible = "qcom,sdm845-gpucc";82 reg = <0x05090000 0x9000>;83 clocks = <&rpmhcc RPMH_CXO_CLK>,84 <&gcc GCC_GPU_GPLL0_CLK_SRC>,85 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;86 clock-names = "bi_tcxo",87 "gcc_gpu_gpll0_clk_src",88 "gcc_gpu_gpll0_div_clk_src";89 #clock-cells = <1>;90 #reset-cells = <1>;91 #power-domain-cells = <1>;92 };93...94