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1# SPDX-License-Identifier: GPL-2.0-only2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/qcom,mmcc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Multimedia Clock & Reset Controller8 9maintainers:10 - Jeffrey Hugo <quic_jhugo@quicinc.com>11 - Taniya Das <quic_tdas@quicinc.com>12 13description: |14 Qualcomm multimedia clock control module provides the clocks, resets and15 power domains.16 17properties:18 compatible:19 enum:20 - qcom,mmcc-apq806421 - qcom,mmcc-apq808422 - qcom,mmcc-msm822623 - qcom,mmcc-msm866024 - qcom,mmcc-msm896025 - qcom,mmcc-msm897426 - qcom,mmcc-msm899227 - qcom,mmcc-msm899428 - qcom,mmcc-msm899629 - qcom,mmcc-msm899830 - qcom,mmcc-sdm63031 - qcom,mmcc-sdm66032 33 clocks:34 minItems: 735 maxItems: 1336 37 clock-names:38 minItems: 739 maxItems: 1340 41 '#clock-cells':42 const: 143 44 '#reset-cells':45 const: 146 47 '#power-domain-cells':48 const: 149 50 reg:51 maxItems: 152 53 protected-clocks:54 description:55 Protected clock specifier list as per common clock binding56 57 vdd-gfx-supply:58 description:59 Regulator supply for the GPU_GX GDSC60 61required:62 - compatible63 - reg64 - '#clock-cells'65 - '#reset-cells'66 - '#power-domain-cells'67 68additionalProperties: false69 70allOf:71 - if:72 properties:73 compatible:74 contains:75 enum:76 - qcom,mmcc-apq806477 - qcom,mmcc-msm896078 then:79 properties:80 clocks:81 items:82 - description: Board PXO source83 - description: PLL 3 clock84 - description: PLL 3 Vote clock85 - description: DSI phy instance 1 dsi clock86 - description: DSI phy instance 1 byte clock87 - description: DSI phy instance 2 dsi clock88 - description: DSI phy instance 2 byte clock89 - description: HDMI phy PLL clock90 91 clock-names:92 items:93 - const: pxo94 - const: pll395 - const: pll8_vote96 - const: dsi1pll97 - const: dsi1pllbyte98 - const: dsi2pll99 - const: dsi2pllbyte100 - const: hdmipll101 102 - if:103 properties:104 compatible:105 contains:106 enum:107 - qcom,mmcc-msm8226108 then:109 properties:110 clocks:111 items:112 - description: Board XO source113 - description: MMSS GPLL0 voted clock114 - description: GPLL0 voted clock115 - description: GPLL1 voted clock116 - description: GFX3D clock source117 - description: DSI phy instance 0 dsi clock118 - description: DSI phy instance 0 byte clock119 120 clock-names:121 items:122 - const: xo123 - const: mmss_gpll0_vote124 - const: gpll0_vote125 - const: gpll1_vote126 - const: gfx3d_clk_src127 - const: dsi0pll128 - const: dsi0pllbyte129 130 - if:131 properties:132 compatible:133 contains:134 enum:135 - qcom,mmcc-msm8974136 then:137 properties:138 clocks:139 items:140 - description: Board XO source141 - description: MMSS GPLL0 voted clock142 - description: GPLL0 voted clock143 - description: GPLL1 voted clock144 - description: GFX3D clock source145 - description: DSI phy instance 0 dsi clock146 - description: DSI phy instance 0 byte clock147 - description: DSI phy instance 1 dsi clock148 - description: DSI phy instance 1 byte clock149 - description: HDMI phy PLL clock150 - description: eDP phy PLL link clock151 - description: eDP phy PLL vco clock152 153 clock-names:154 items:155 - const: xo156 - const: mmss_gpll0_vote157 - const: gpll0_vote158 - const: gpll1_vote159 - const: gfx3d_clk_src160 - const: dsi0pll161 - const: dsi0pllbyte162 - const: dsi1pll163 - const: dsi1pllbyte164 - const: hdmipll165 - const: edp_link_clk166 - const: edp_vco_div167 168 - if:169 properties:170 compatible:171 contains:172 enum:173 - qcom,mmcc-apq8084174 then:175 properties:176 clocks:177 items:178 - description: Board XO source179 - description: Board sleep source180 - description: MMSS GPLL0 voted clock181 - description: GPLL0 clock182 - description: GPLL0 voted clock183 - description: GPLL1 clock184 - description: DSI phy instance 0 dsi clock185 - description: DSI phy instance 0 byte clock186 - description: DSI phy instance 1 dsi clock187 - description: DSI phy instance 1 byte clock188 - description: HDMI phy PLL clock189 - description: eDP phy PLL link clock190 - description: eDP phy PLL vco clock191 192 clock-names:193 items:194 - const: xo195 - const: sleep_clk196 - const: mmss_gpll0_vote197 - const: gpll0198 - const: gpll0_vote199 - const: gpll1200 - const: dsi0pll201 - const: dsi0pllbyte202 - const: dsi1pll203 - const: dsi1pllbyte204 - const: hdmipll205 - const: edp_link_clk206 - const: edp_vco_div207 208 - if:209 properties:210 compatible:211 contains:212 enum:213 - qcom,mmcc-msm8994214 - qcom,mmcc-msm8998215 - qcom,mmcc-sdm630216 - qcom,mmcc-sdm660217 then:218 required:219 - clocks220 - clock-names221 222 - if:223 properties:224 compatible:225 contains:226 const: qcom,mmcc-msm8994227 then:228 properties:229 clocks:230 items:231 - description: Board XO source232 - description: Global PLL 0 clock233 - description: MMSS NoC AHB clock234 - description: GFX3D clock235 - description: DSI phy instance 0 dsi clock236 - description: DSI phy instance 0 byte clock237 - description: DSI phy instance 1 dsi clock238 - description: DSI phy instance 1 byte clock239 - description: HDMI phy PLL clock240 241 clock-names:242 items:243 - const: xo244 - const: gpll0245 - const: mmssnoc_ahb246 - const: oxili_gfx3d_clk_src247 - const: dsi0pll248 - const: dsi0pllbyte249 - const: dsi1pll250 - const: dsi1pllbyte251 - const: hdmipll252 253 - if:254 properties:255 compatible:256 contains:257 const: qcom,mmcc-msm8996258 then:259 properties:260 clocks:261 items:262 - description: Board XO source263 - description: Global PLL 0 clock264 - description: MMSS NoC AHB clock265 - description: DSI phy instance 0 dsi clock266 - description: DSI phy instance 0 byte clock267 - description: DSI phy instance 1 dsi clock268 - description: DSI phy instance 1 byte clock269 - description: HDMI phy PLL clock270 271 clock-names:272 items:273 - const: xo274 - const: gpll0275 - const: gcc_mmss_noc_cfg_ahb_clk276 - const: dsi0pll277 - const: dsi0pllbyte278 - const: dsi1pll279 - const: dsi1pllbyte280 - const: hdmipll281 282 - if:283 properties:284 compatible:285 contains:286 const: qcom,mmcc-msm8998287 then:288 properties:289 clocks:290 items:291 - description: Board XO source292 - description: Global PLL 0 clock293 - description: DSI phy instance 0 dsi clock294 - description: DSI phy instance 0 byte clock295 - description: DSI phy instance 1 dsi clock296 - description: DSI phy instance 1 byte clock297 - description: HDMI phy PLL clock298 - description: DisplayPort phy PLL link clock299 - description: DisplayPort phy PLL vco clock300 - description: Global PLL 0 DIV clock301 302 clock-names:303 items:304 - const: xo305 - const: gpll0306 - const: dsi0dsi307 - const: dsi0byte308 - const: dsi1dsi309 - const: dsi1byte310 - const: hdmipll311 - const: dplink312 - const: dpvco313 - const: gpll0_div314 315 - if:316 properties:317 compatible:318 contains:319 enum:320 - qcom,mmcc-sdm630321 - qcom,mmcc-sdm660322 then:323 properties:324 clocks:325 items:326 - description: Board XO source327 - description: Board sleep source328 - description: Global PLL 0 clock329 - description: Global PLL 0 DIV clock330 - description: DSI phy instance 0 dsi clock331 - description: DSI phy instance 0 byte clock332 - description: DSI phy instance 1 dsi clock333 - description: DSI phy instance 1 byte clock334 - description: DisplayPort phy PLL link clock335 - description: DisplayPort phy PLL vco clock336 337 clock-names:338 items:339 - const: xo340 - const: sleep_clk341 - const: gpll0342 - const: gpll0_div343 - const: dsi0pll344 - const: dsi0pllbyte345 - const: dsi1pll346 - const: dsi1pllbyte347 - const: dp_link_2x_clk_divsel_five348 - const: dp_vco_divided_clk_src_mux349 350examples:351 # Example for MMCC for MSM8960:352 - |353 clock-controller@4000000 {354 compatible = "qcom,mmcc-msm8960";355 reg = <0x4000000 0x1000>;356 #clock-cells = <1>;357 #reset-cells = <1>;358 #power-domain-cells = <1>;359 };360...361