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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/qcom,qca8k-nsscc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm NSS Clock & Reset Controller on QCA8386/QCA80848 9maintainers:10 - Bjorn Andersson <andersson@kernel.org>11 - Luo Jie <quic_luoj@quicinc.com>12 13description: |14 Qualcomm NSS clock control module provides the clocks and resets15 on QCA8386(switch mode)/QCA8084(PHY mode)16 17 See also::18 include/dt-bindings/clock/qcom,qca8k-nsscc.h19 include/dt-bindings/reset/qcom,qca8k-nsscc.h20 21properties:22 compatible:23 oneOf:24 - const: qcom,qca8084-nsscc25 - items:26 - enum:27 - qcom,qca8082-nsscc28 - qcom,qca8085-nsscc29 - qcom,qca8384-nsscc30 - qcom,qca8385-nsscc31 - qcom,qca8386-nsscc32 - const: qcom,qca8084-nsscc33 34 clocks:35 items:36 - description: Chip reference clock source37 - description: UNIPHY0 RX 312P5M/125M clock source38 - description: UNIPHY0 TX 312P5M/125M clock source39 - description: UNIPHY1 RX 312P5M/125M clock source40 - description: UNIPHY1 TX 312P5M/125M clock source41 - description: UNIPHY1 RX 312P5M clock source42 - description: UNIPHY1 TX 312P5M clock source43 44 reg:45 items:46 - description: MDIO bus address for Clock & Reset Controller register47 48 reset-gpios:49 description: GPIO connected to the chip50 maxItems: 151 52required:53 - compatible54 - clocks55 - reg56 - reset-gpios57 58allOf:59 - $ref: qcom,gcc.yaml#60 61unevaluatedProperties: false62 63examples:64 - |65 #include <dt-bindings/gpio/gpio.h>66 mdio {67 #address-cells = <1>;68 #size-cells = <0>;69 70 clock-controller@18 {71 compatible = "qcom,qca8084-nsscc";72 reg = <0x18>;73 reset-gpios = <&tlmm 51 GPIO_ACTIVE_LOW>;74 clocks = <&pcs0_pll>,75 <&qca8k_uniphy0_rx>,76 <&qca8k_uniphy0_tx>,77 <&qca8k_uniphy1_rx>,78 <&qca8k_uniphy1_tx>,79 <&qca8k_uniphy1_rx312p5m>,80 <&qca8k_uniphy1_tx312p5m>;81 #clock-cells = <1>;82 #reset-cells = <1>;83 #power-domain-cells = <1>;84 };85 };86...87