76 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/qcom,qcm2290-dispcc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Display Clock & Reset Controller on QCM22908 9maintainers:10 - Loic Poulain <loic.poulain@linaro.org>11 12description: |13 Qualcomm display clock control module provides the clocks, resets and power14 domains on qcm2290.15 16 See also:: include/dt-bindings/clock/qcom,dispcc-qcm2290.h17 18properties:19 compatible:20 const: qcom,qcm2290-dispcc21 22 clocks:23 items:24 - description: Board XO source25 - description: Board active-only XO source26 - description: GPLL0 source from GCC27 - description: GPLL0 div source from GCC28 - description: Byte clock from DSI PHY29 - description: Pixel clock from DSI PHY30 31 clock-names:32 items:33 - const: bi_tcxo34 - const: bi_tcxo_ao35 - const: gcc_disp_gpll0_clk_src36 - const: gcc_disp_gpll0_div_clk_src37 - const: dsi0_phy_pll_out_byteclk38 - const: dsi0_phy_pll_out_dsiclk39 40required:41 - compatible42 - clocks43 - clock-names44 - '#power-domain-cells'45 46allOf:47 - $ref: qcom,gcc.yaml#48 49unevaluatedProperties: false50 51examples:52 - |53 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>54 #include <dt-bindings/clock/qcom,gcc-qcm2290.h>55 #include <dt-bindings/clock/qcom,rpmcc.h>56 clock-controller@5f00000 {57 compatible = "qcom,qcm2290-dispcc";58 reg = <0x5f00000 0x20000>;59 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,60 <&rpmcc RPM_SMD_XO_A_CLK_SRC>,61 <&gcc GCC_DISP_GPLL0_CLK_SRC>,62 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,63 <&dsi0_phy 0>,64 <&dsi0_phy 1>;65 clock-names = "bi_tcxo",66 "bi_tcxo_ao",67 "gcc_disp_gpll0_clk_src",68 "gcc_disp_gpll0_div_clk_src",69 "dsi0_phy_pll_out_byteclk",70 "dsi0_phy_pll_out_dsiclk";71 #clock-cells = <1>;72 #reset-cells = <1>;73 #power-domain-cells = <1>;74 };75...76