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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/qcom,qcm2290-gpucc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Graphics Clock & Reset Controller on QCM22908 9maintainers:10 - Konrad Dybcio <konradybcio@kernel.org>11 12description: |13 Qualcomm graphics clock control module provides the clocks, resets and power14 domains on Qualcomm SoCs.15 16 See also::17 include/dt-bindings/clock/qcom,qcm2290-gpucc.h18 19properties:20 compatible:21 const: qcom,qcm2290-gpucc22 23 reg:24 maxItems: 125 26 clocks:27 items:28 - description: AHB interface clock,29 - description: SoC CXO clock30 - description: GPLL0 main branch source31 - description: GPLL0 div branch source32 33 power-domains:34 description:35 A phandle and PM domain specifier for the CX power domain.36 maxItems: 137 38 required-opps:39 description:40 A phandle to an OPP node describing required CX performance point.41 maxItems: 142 43required:44 - compatible45 - clocks46 - power-domains47 48allOf:49 - $ref: qcom,gcc.yaml#50 51unevaluatedProperties: false52 53examples:54 - |55 #include <dt-bindings/clock/qcom,gcc-qcm2290.h>56 #include <dt-bindings/clock/qcom,rpmcc.h>57 #include <dt-bindings/power/qcom-rpmpd.h>58 59 soc {60 #address-cells = <2>;61 #size-cells = <2>;62 63 clock-controller@5990000 {64 compatible = "qcom,qcm2290-gpucc";65 reg = <0x0 0x05990000 0x0 0x9000>;66 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,67 <&rpmcc RPM_SMD_XO_CLK_SRC>,68 <&gcc GCC_GPU_GPLL0_CLK_SRC>,69 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;70 power-domains = <&rpmpd QCM2290_VDDCX>;71 required-opps = <&rpmpd_opp_low_svs>;72 #clock-cells = <1>;73 #reset-cells = <1>;74 #power-domain-cells = <1>;75 };76 };77...78