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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/qcom,qdu1000-gcc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Global Clock & Reset Controller for QDU1000 and QRU10008 9maintainers:10 - Taniya Das <quic_tdas@quicinc.com>11 - Imran Shaik <quic_imrashai@quicinc.com>12 13description: |14 Qualcomm global clock control module which supports the clocks, resets and15 power domains on QDU1000 and QRU100016 17 See also:: include/dt-bindings/clock/qcom,qdu1000-gcc.h18 19properties:20 compatible:21 const: qcom,qdu1000-gcc22 23 clocks:24 items:25 - description: Board XO source26 - description: Sleep clock source27 - description: PCIE 0 Pipe clock source28 - description: PCIE 0 Phy Auxiliary clock source29 - description: USB3 Phy wrapper pipe clock source30 31required:32 - compatible33 - clocks34 - '#power-domain-cells'35 36allOf:37 - $ref: qcom,gcc.yaml#38 39unevaluatedProperties: false40 41examples:42 - |43 #include <dt-bindings/clock/qcom,rpmh.h>44 clock-controller@100000 {45 compatible = "qcom,qdu1000-gcc";46 reg = <0x00100000 0x001f4200>;47 clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,48 <&pcie_0_pipe_clk>, <&pcie_0_phy_aux_clk>,49 <&usb3_phy_wrapper_pipe_clk>;50 #clock-cells = <1>;51 #reset-cells = <1>;52 #power-domain-cells = <1>;53 };54