90 lines · yaml
1# SPDX-License-Identifier: GPL-2.0-only2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/qcom,sdm845-dispcc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Display Clock & Reset Controller on SDM8458 9maintainers:10 - Taniya Das <quic_tdas@quicinc.com>11 12description: |13 Qualcomm display clock control module provides the clocks, resets and power14 domains on SDM845.15 16 See also:: include/dt-bindings/clock/qcom,dispcc-sdm845.h17 18properties:19 compatible:20 const: qcom,sdm845-dispcc21 22 # NOTE: sdm845.dtsi existed for quite some time and specified no clocks.23 # The code had to use hardcoded mechanisms to find the input clocks.24 # New dts files should have these clocks.25 clocks:26 items:27 - description: Board XO source28 - description: GPLL0 source from GCC29 - description: GPLL0 div source from GCC30 - description: Byte clock from DSI PHY031 - description: Pixel clock from DSI PHY032 - description: Byte clock from DSI PHY133 - description: Pixel clock from DSI PHY134 - description: Link clock from DP PHY35 - description: VCO DIV clock from DP PHY36 37 clock-names:38 items:39 - const: bi_tcxo40 - const: gcc_disp_gpll0_clk_src41 - const: gcc_disp_gpll0_div_clk_src42 - const: dsi0_phy_pll_out_byteclk43 - const: dsi0_phy_pll_out_dsiclk44 - const: dsi1_phy_pll_out_byteclk45 - const: dsi1_phy_pll_out_dsiclk46 - const: dp_link_clk_divsel_ten47 - const: dp_vco_divided_clk_src_mux48 49required:50 - compatible51 - clocks52 - clock-names53 - '#power-domain-cells'54 55allOf:56 - $ref: qcom,gcc.yaml#57 58unevaluatedProperties: false59 60examples:61 - |62 #include <dt-bindings/clock/qcom,gcc-sdm845.h>63 #include <dt-bindings/clock/qcom,rpmh.h>64 clock-controller@af00000 {65 compatible = "qcom,sdm845-dispcc";66 reg = <0x0af00000 0x10000>;67 clocks = <&rpmhcc RPMH_CXO_CLK>,68 <&gcc GCC_DISP_GPLL0_CLK_SRC>,69 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,70 <&dsi0_phy 0>,71 <&dsi0_phy 1>,72 <&dsi1_phy 0>,73 <&dsi1_phy 1>,74 <&dp_phy 0>,75 <&dp_phy 1>;76 clock-names = "bi_tcxo",77 "gcc_disp_gpll0_clk_src",78 "gcc_disp_gpll0_div_clk_src",79 "dsi0_phy_pll_out_byteclk",80 "dsi0_phy_pll_out_dsiclk",81 "dsi1_phy_pll_out_byteclk",82 "dsi1_phy_pll_out_dsiclk",83 "dp_link_clk_divsel_ten",84 "dp_vco_divided_clk_src_mux";85 #clock-cells = <1>;86 #reset-cells = <1>;87 #power-domain-cells = <1>;88 };89...90