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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/qcom,sm4450-dispcc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Display Clock & Reset Controller on SM44508 9maintainers:10 - Ajit Pandey <quic_ajipan@quicinc.com>11 - Taniya Das <quic_tdas@quicinc.com>12 13description: |14 Qualcomm display clock control module provides the clocks, resets and power15 domains on SM445016 17 See also:: include/dt-bindings/clock/qcom,sm4450-dispcc.h18 19properties:20 compatible:21 const: qcom,sm4450-dispcc22 23 reg:24 maxItems: 125 26 clocks:27 items:28 - description: Board XO source29 - description: Board active XO source30 - description: Display AHB clock source from GCC31 - description: sleep clock source32 - description: Byte clock from DSI PHY033 - description: Pixel clock from DSI PHY034 35 '#clock-cells':36 const: 137 38 '#reset-cells':39 const: 140 41 '#power-domain-cells':42 const: 143 44required:45 - compatible46 - reg47 - clocks48 - '#clock-cells'49 - '#reset-cells'50 - '#power-domain-cells'51 52additionalProperties: false53 54examples:55 - |56 #include <dt-bindings/clock/qcom,rpmh.h>57 #include <dt-bindings/clock/qcom,sm4450-gcc.h>58 clock-controller@af00000 {59 compatible = "qcom,sm4450-dispcc";60 reg = <0x0af00000 0x20000>;61 clocks = <&rpmhcc RPMH_CXO_CLK>,62 <&rpmhcc RPMH_CXO_CLK_A>,63 <&gcc GCC_DISP_AHB_CLK>,64 <&sleep_clk>,65 <&dsi0_phy_pll_out_byteclk>,66 <&dsi0_phy_pll_out_dsiclk>;67 #clock-cells = <1>;68 #reset-cells = <1>;69 #power-domain-cells = <1>;70 };71...72