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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/qcom,sm4450-gcc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Global Clock & Reset Controller on SM44508 9maintainers:10 - Ajit Pandey <quic_ajipan@quicinc.com>11 - Taniya Das <quic_tdas@quicinc.com>12 13description: |14 Qualcomm global clock control module provides the clocks, resets and power15 domains on SM445016 17 See also:: include/dt-bindings/clock/qcom,sm4450-gcc.h18 19properties:20 compatible:21 const: qcom,sm4450-gcc22 23 clocks:24 items:25 - description: Board XO source26 - description: Sleep clock source27 - description: UFS Phy Rx symbol 0 clock source28 - description: UFS Phy Rx symbol 1 clock source29 - description: UFS Phy Tx symbol 0 clock source30 - description: USB3 Phy wrapper pipe clock source31 32required:33 - compatible34 - clocks35 - '#power-domain-cells'36 37allOf:38 - $ref: qcom,gcc.yaml#39 40unevaluatedProperties: false41 42examples:43 - |44 #include <dt-bindings/clock/qcom,rpmh.h>45 clock-controller@100000 {46 compatible = "qcom,sm4450-gcc";47 reg = <0x00100000 0x001f4200>;48 clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,49 <&ufs_mem_phy 0>, <&ufs_mem_phy 1>,50 <&ufs_mem_phy 2>, <&usb_1_qmpphy>;51 #clock-cells = <1>;52 #reset-cells = <1>;53 #power-domain-cells = <1>;54 };55 56...57