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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/qcom,sm6115-dispcc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Display Clock Controller for SM61158 9maintainers:10 - Bjorn Andersson <andersson@kernel.org>11 12description: |13 Qualcomm display clock control module provides the clocks and power domains14 on SM6115.15 16 See also:: include/dt-bindings/clock/qcom,sm6115-dispcc.h17 18properties:19 compatible:20 enum:21 - qcom,sm6115-dispcc22 23 clocks:24 items:25 - description: Board XO source26 - description: Board sleep clock27 - description: Byte clock from DSI PHY028 - description: Pixel clock from DSI PHY029 - description: GPLL0 DISP DIV clock from GCC30 31required:32 - compatible33 - clocks34 - '#power-domain-cells'35 36allOf:37 - $ref: qcom,gcc.yaml#38 39unevaluatedProperties: false40 41examples:42 - |43 #include <dt-bindings/clock/qcom,rpmcc.h>44 #include <dt-bindings/clock/qcom,gcc-sm6115.h>45 clock-controller@5f00000 {46 compatible = "qcom,sm6115-dispcc";47 reg = <0x5f00000 0x20000>;48 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,49 <&sleep_clk>,50 <&dsi0_phy 0>,51 <&dsi0_phy 1>,52 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;53 #clock-cells = <1>;54 #reset-cells = <1>;55 #power-domain-cells = <1>;56 };57...58