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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/qcom,sm6375-dispcc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Display Clock & Reset Controller on SM63758 9maintainers:10 - Konrad Dybcio <konradybcio@kernel.org>11 12description: |13 Qualcomm display clock control module provides the clocks, resets and power14 domains on SM6375.15 16 See also:: include/dt-bindings/clock/qcom,dispcc-sm6375.h17 18allOf:19 - $ref: qcom,gcc.yaml#20 21properties:22 compatible:23 const: qcom,sm6375-dispcc24 25 clocks:26 items:27 - description: Board XO source28 - description: GPLL0 source from GCC29 - description: Byte clock from DSI PHY30 - description: Pixel clock from DSI PHY31 32required:33 - compatible34 - clocks35 36unevaluatedProperties: false37 38examples:39 - |40 #include <dt-bindings/clock/qcom,sm6375-gcc.h>41 #include <dt-bindings/clock/qcom,rpmh.h>42 43 clock-controller@5f00000 {44 compatible = "qcom,sm6375-dispcc";45 reg = <0x05f00000 0x20000>;46 clocks = <&rpmhcc RPMH_CXO_CLK>,47 <&gcc GCC_DISP_GPLL0_CLK_SRC>,48 <&dsi_phy 0>,49 <&dsi_phy 1>;50 #clock-cells = <1>;51 #reset-cells = <1>;52 #power-domain-cells = <1>;53 };54...55