70 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/qcom,sm8450-gpucc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Graphics Clock & Reset Controller on SM84508 9maintainers:10 - Konrad Dybcio <konradybcio@kernel.org>11 12description: |13 Qualcomm graphics clock control module provides the clocks, resets and power14 domains on Qualcomm SoCs.15 16 See also::17 include/dt-bindings/clock/qcom,sm4450-gpucc.h18 include/dt-bindings/clock/qcom,sm8450-gpucc.h19 include/dt-bindings/clock/qcom,sm8550-gpucc.h20 include/dt-bindings/reset/qcom,sm8450-gpucc.h21 include/dt-bindings/reset/qcom,sm8650-gpucc.h22 include/dt-bindings/reset/qcom,x1e80100-gpucc.h23 24properties:25 compatible:26 enum:27 - qcom,sm4450-gpucc28 - qcom,sm8450-gpucc29 - qcom,sm8550-gpucc30 - qcom,sm8650-gpucc31 - qcom,x1e80100-gpucc32 33 clocks:34 items:35 - description: Board XO source36 - description: GPLL0 main branch source37 - description: GPLL0 div branch source38 39required:40 - compatible41 - clocks42 - '#power-domain-cells'43 44allOf:45 - $ref: qcom,gcc.yaml#46 47unevaluatedProperties: false48 49examples:50 - |51 #include <dt-bindings/clock/qcom,gcc-sm8450.h>52 #include <dt-bindings/clock/qcom,rpmh.h>53 54 soc {55 #address-cells = <2>;56 #size-cells = <2>;57 58 clock-controller@3d90000 {59 compatible = "qcom,sm8450-gpucc";60 reg = <0 0x03d90000 0 0xa000>;61 clocks = <&rpmhcc RPMH_CXO_CLK>,62 <&gcc GCC_GPU_GPLL0_CLK_SRC>,63 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;64 #clock-cells = <1>;65 #reset-cells = <1>;66 #power-domain-cells = <1>;67 };68 };69...70