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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/qcom,sm8550-dispcc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Display Clock & Reset Controller for SM85508 9maintainers:10 - Bjorn Andersson <andersson@kernel.org>11 - Neil Armstrong <neil.armstrong@linaro.org>12 13description: |14 Qualcomm display clock control module provides the clocks, resets and power15 domains on SM8550.16 17 See also:18 - include/dt-bindings/clock/qcom,sm8550-dispcc.h19 - include/dt-bindings/clock/qcom,sm8650-dispcc.h20 - include/dt-bindings/clock/qcom,x1e80100-dispcc.h21 22properties:23 compatible:24 enum:25 - qcom,sm8550-dispcc26 - qcom,sm8650-dispcc27 - qcom,x1e80100-dispcc28 29 clocks:30 items:31 - description: Board XO source32 - description: Board Always On XO source33 - description: Display's AHB clock34 - description: sleep clock35 - description: Byte clock from DSI PHY036 - description: Pixel clock from DSI PHY037 - description: Byte clock from DSI PHY138 - description: Pixel clock from DSI PHY139 - description: Link clock from DP PHY040 - description: VCO DIV clock from DP PHY041 - description: Link clock from DP PHY142 - description: VCO DIV clock from DP PHY143 - description: Link clock from DP PHY244 - description: VCO DIV clock from DP PHY245 - description: Link clock from DP PHY346 - description: VCO DIV clock from DP PHY347 48 power-domains:49 description:50 A phandle and PM domain specifier for the MMCX power domain.51 maxItems: 152 53 required-opps:54 description:55 A phandle to an OPP node describing required MMCX performance point.56 maxItems: 157 58required:59 - compatible60 - clocks61 - '#power-domain-cells'62 63allOf:64 - $ref: qcom,gcc.yaml#65 66unevaluatedProperties: false67 68examples:69 - |70 #include <dt-bindings/clock/qcom,sm8550-gcc.h>71 #include <dt-bindings/clock/qcom,rpmh.h>72 #include <dt-bindings/power/qcom,rpmhpd.h>73 clock-controller@af00000 {74 compatible = "qcom,sm8550-dispcc";75 reg = <0x0af00000 0x10000>;76 clocks = <&rpmhcc RPMH_CXO_CLK>,77 <&rpmhcc RPMH_CXO_CLK_A>,78 <&gcc GCC_DISP_AHB_CLK>,79 <&sleep_clk>,80 <&dsi0_phy 0>,81 <&dsi0_phy 1>,82 <&dsi1_phy 0>,83 <&dsi1_phy 1>,84 <&dp0_phy 0>,85 <&dp0_phy 1>,86 <&dp1_phy 0>,87 <&dp1_phy 1>,88 <&dp2_phy 0>,89 <&dp2_phy 1>,90 <&dp3_phy 0>,91 <&dp3_phy 1>;92 #clock-cells = <1>;93 #reset-cells = <1>;94 #power-domain-cells = <1>;95 power-domains = <&rpmhpd RPMHPD_MMCX>;96 required-opps = <&rpmhpd_opp_low_svs>;97 };98...99