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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/qcom,sm8550-gcc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Global Clock & Reset Controller on SM85508 9maintainers:10 - Bjorn Andersson <andersson@kernel.org>11 12description: |13 Qualcomm global clock control module provides the clocks, resets and power14 domains on SM855015 16 See also:: include/dt-bindings/clock/qcom,sm8550-gcc.h17 18properties:19 compatible:20 const: qcom,sm8550-gcc21 22 clocks:23 items:24 - description: Board XO source25 - description: Sleep clock source26 - description: PCIE 0 Pipe clock source27 - description: PCIE 1 Pipe clock source28 - description: PCIE 1 Phy Auxiliary clock source29 - description: UFS Phy Rx symbol 0 clock source30 - description: UFS Phy Rx symbol 1 clock source31 - description: UFS Phy Tx symbol 0 clock source32 - description: USB3 Phy wrapper pipe clock source33 34required:35 - compatible36 - clocks37 - '#power-domain-cells'38 39allOf:40 - $ref: qcom,gcc.yaml#41 42unevaluatedProperties: false43 44examples:45 - |46 #include <dt-bindings/clock/qcom,rpmh.h>47 clock-controller@100000 {48 compatible = "qcom,sm8550-gcc";49 reg = <0x00100000 0x001f4200>;50 clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,51 <&pcie0_phy>,52 <&pcie1_phy>,53 <&pcie_1_phy_aux_clk>,54 <&ufs_mem_phy 0>,55 <&ufs_mem_phy 1>,56 <&ufs_mem_phy 2>,57 <&usb_1_qmpphy>;58 #clock-cells = <1>;59 #reset-cells = <1>;60 #power-domain-cells = <1>;61 };62 63...64