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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/qcom,x1e80100-gcc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Global Clock & Reset Controller on X1E801008 9maintainers:10 - Rajendra Nayak <quic_rjendra@quicinc.com>11 12description: |13 Qualcomm global clock control module provides the clocks, resets and power14 domains on X1E8010015 16 See also:: include/dt-bindings/clock/qcom,x1e80100-gcc.h17 18properties:19 compatible:20 const: qcom,x1e80100-gcc21 22 clocks:23 items:24 - description: Board XO source25 - description: Sleep clock source26 - description: PCIe 3 pipe clock27 - description: PCIe 4 pipe clock28 - description: PCIe 5 pipe clock29 - description: PCIe 6a pipe clock30 - description: PCIe 6b pipe clock31 - description: USB QMP Phy 0 clock source32 - description: USB QMP Phy 1 clock source33 - description: USB QMP Phy 2 clock source34 35 power-domains:36 description:37 A phandle and PM domain specifier for the CX power domain.38 maxItems: 139 40required:41 - compatible42 - clocks43 - power-domains44 - '#power-domain-cells'45 46allOf:47 - $ref: qcom,gcc.yaml#48 49unevaluatedProperties: false50 51examples:52 - |53 #include <dt-bindings/power/qcom,rpmhpd.h>54 clock-controller@100000 {55 compatible = "qcom,x1e80100-gcc";56 reg = <0x00100000 0x200000>;57 clocks = <&bi_tcxo_div2>,58 <&sleep_clk>,59 <&pcie3_phy>,60 <&pcie4_phy>,61 <&pcie5_phy>,62 <&pcie6a_phy>,63 <&pcie6b_phy>,64 <&usb_1_ss0_qmpphy 0>,65 <&usb_1_ss1_qmpphy 1>,66 <&usb_1_ss2_qmpphy 2>;67 power-domains = <&rpmhpd RPMHPD_CX>;68 #clock-cells = <1>;69 #reset-cells = <1>;70 #power-domain-cells = <1>;71 };72 73...74