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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/renesas,5p35023.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Renesas 5p35023 VersaClock 3 programmable I2C clock generator8 9maintainers:10 - Biju Das <biju.das.jz@bp.renesas.com>11 12description: |13 The 5P35023 is a VersaClock programmable clock generator and14 is designed for low-power, consumer, and high-performance PCI15 express applications. The 5P35023 device is a three PLL16 architecture design, and each PLL is individually programmable17 and allowing for up to 6 unique frequency outputs.18 19 An internal OTP memory allows the user to store the configuration20 in the device. After power up, the user can change the device register21 settings through the I2C interface when I2C mode is selected.22 23 The driver can read a full register map from the DT, and will use that24 register map to initialize the attached part (via I2C) when the system25 boots. Any configuration not supported by the common clock framework26 must be done via the full register map, including optimized settings.27 28 Link to datasheet:29 https://www.renesas.com/us/en/products/clocks-timing/clock-generation/programmable-clocks/5p35023-versaclock-3s-programmable-clock-generator30 31properties:32 compatible:33 enum:34 - renesas,5p3502335 36 reg:37 maxItems: 138 39 '#clock-cells':40 description:41 The index in the assigned-clocks is mapped to the output clock as below42 0 - REF, 1 - SE1, 2 - SE2, 3 - SE3, 4 - DIFF1, 5 - DIFF2.43 const: 144 45 clocks:46 maxItems: 147 48 renesas,settings:49 description: Optional, complete register map of the device.50 Optimized settings for the device must be provided in full51 and are written during initialization.52 $ref: /schemas/types.yaml#/definitions/uint8-array53 maxItems: 3754 55required:56 - compatible57 - reg58 - '#clock-cells'59 - clocks60 61additionalProperties: false62 63examples:64 - |65 i2c {66 #address-cells = <1>;67 #size-cells = <0>;68 69 versa3: clock-generator@68 {70 compatible = "renesas,5p35023";71 reg = <0x68>;72 #clock-cells = <1>;73 74 clocks = <&x1>;75 76 renesas,settings = [77 80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf78 00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b679 80 b0 45 c4 9580 ];81 82 assigned-clocks = <&versa3 0>, <&versa3 1>,83 <&versa3 2>, <&versa3 3>,84 <&versa3 4>, <&versa3 5>;85 assigned-clock-rates = <24000000>, <11289600>,86 <11289600>, <12000000>,87 <25000000>, <12288000>;88 };89 };90