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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/renesas,cpg-clocks.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Renesas Clock Pulse Generator (CPG)8 9maintainers:10 - Geert Uytterhoeven <geert+renesas@glider.be>11 12description:13 The Clock Pulse Generator (CPG) generates core clocks for the SoC. It14 includes PLLs, and fixed and variable ratio dividers.15 16 The CPG may also provide a Clock Domain for SoC devices, in combination with17 the CPG Module Stop (MSTP) Clocks.18 19properties:20 compatible:21 oneOf:22 - const: renesas,r8a73a4-cpg-clocks # R-Mobile APE623 - const: renesas,r8a7740-cpg-clocks # R-Mobile A124 - const: renesas,r8a7778-cpg-clocks # R-Car M125 - const: renesas,r8a7779-cpg-clocks # R-Car H126 - items:27 - enum:28 - renesas,r7s72100-cpg-clocks # RZ/A1H29 - const: renesas,rz-cpg-clocks # RZ/A130 - const: renesas,sh73a0-cpg-clocks # SH-Mobile AG531 32 reg:33 maxItems: 134 35 clocks:36 minItems: 137 maxItems: 338 39 '#clock-cells':40 const: 141 42 clock-output-names:43 minItems: 344 maxItems: 1745 46 renesas,mode:47 description: Board-specific settings of the MD_CK* bits on R-Mobile A148 $ref: /schemas/types.yaml#/definitions/uint3249 minimum: 050 maximum: 751 52 '#power-domain-cells':53 const: 054 55required:56 - compatible57 - reg58 - clocks59 - '#clock-cells'60 - clock-output-names61 62allOf:63 - if:64 properties:65 compatible:66 contains:67 const: renesas,r8a73a4-cpg-clocks68 then:69 properties:70 clocks:71 items:72 - description: extal173 - description: extal274 75 clock-output-names:76 items:77 - const: main78 - const: pll079 - const: pll180 - const: pll281 - const: pll2s82 - const: pll2h83 - const: z84 - const: z285 - const: i86 - const: m387 - const: b88 - const: m189 - const: m290 - const: zx91 - const: zs92 - const: hp93 94 - if:95 properties:96 compatible:97 contains:98 const: renesas,r8a7740-cpg-clocks99 then:100 properties:101 clocks:102 items:103 - description: extal1104 - description: extal2105 - description: extalr106 107 clock-output-names:108 items:109 - const: system110 - const: pllc0111 - const: pllc1112 - const: pllc2113 - const: r114 - const: usb24s115 - const: i116 - const: zg117 - const: b118 - const: m1119 - const: hp120 - const: hpp121 - const: usbp122 - const: s123 - const: zb124 - const: m3125 - const: cp126 127 required:128 - renesas,mode129 130 - if:131 properties:132 compatible:133 contains:134 const: renesas,r8a7778-cpg-clocks135 then:136 properties:137 clocks:138 maxItems: 1139 140 clock-output-names:141 items:142 - const: plla143 - const: pllb144 - const: b145 - const: out146 - const: p147 - const: s148 - const: s1149 150 - if:151 properties:152 compatible:153 contains:154 const: renesas,r8a7779-cpg-clocks155 then:156 properties:157 clocks:158 maxItems: 1159 160 clock-output-names:161 items:162 - const: plla163 - const: z164 - const: zs165 - const: s166 - const: s1167 - const: p168 - const: b169 - const: out170 171 - if:172 properties:173 compatible:174 contains:175 const: renesas,r7s72100-cpg-clocks176 then:177 properties:178 clocks:179 items:180 - description: extal1181 - description: usb_x1182 183 clock-output-names:184 items:185 - const: pll186 - const: i187 - const: g188 189 - if:190 properties:191 compatible:192 contains:193 const: renesas,sh73a0-cpg-clocks194 then:195 properties:196 clocks:197 items:198 - description: extal1199 - description: extal2200 201 clock-output-names:202 items:203 - const: main204 - const: pll0205 - const: pll1206 - const: pll2207 - const: pll3208 - const: dsi0phy209 - const: dsi1phy210 - const: zg211 - const: m3212 - const: b213 - const: m1214 - const: m2215 - const: z216 - const: zx217 - const: hp218 219 - if:220 properties:221 compatible:222 contains:223 enum:224 - renesas,r8a7778-cpg-clocks225 - renesas,r8a7779-cpg-clocks226 - renesas,rz-cpg-clocks227 then:228 required:229 - '#power-domain-cells'230 231additionalProperties: false232 233examples:234 - |235 #include <dt-bindings/clock/r8a7740-clock.h>236 cpg_clocks: cpg_clocks@e6150000 {237 compatible = "renesas,r8a7740-cpg-clocks";238 reg = <0xe6150000 0x10000>;239 clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;240 #clock-cells = <1>;241 clock-output-names = "system", "pllc0", "pllc1", "pllc2", "r",242 "usb24s", "i", "zg", "b", "m1", "hp", "hpp",243 "usbp", "s", "zb", "m3", "cp";244 renesas,mode = <0x05>;245 };246