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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Renesas Clock Pulse Generator / Module Standby and Software Reset8 9maintainers:10 - Geert Uytterhoeven <geert+renesas@glider.be>11 12description: |13 On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)14 and MSSR (Module Standby and Software Reset) blocks are intimately connected,15 and share the same register block.16 17 They provide the following functionalities:18 - The CPG block generates various core clocks,19 - The MSSR block provides two functions:20 1. Module Standby, providing a Clock Domain to control the clock supply21 to individual SoC devices,22 2. Reset Control, to perform a software reset of individual SoC devices.23 24properties:25 compatible:26 enum:27 - renesas,r7s9210-cpg-mssr # RZ/A228 - renesas,r8a7742-cpg-mssr # RZ/G1H29 - renesas,r8a7743-cpg-mssr # RZ/G1M30 - renesas,r8a7744-cpg-mssr # RZ/G1N31 - renesas,r8a7745-cpg-mssr # RZ/G1E32 - renesas,r8a77470-cpg-mssr # RZ/G1C33 - renesas,r8a774a1-cpg-mssr # RZ/G2M34 - renesas,r8a774a3-cpg-mssr # RZ/G2M v3.035 - renesas,r8a774b1-cpg-mssr # RZ/G2N36 - renesas,r8a774c0-cpg-mssr # RZ/G2E37 - renesas,r8a774e1-cpg-mssr # RZ/G2H38 - renesas,r8a7790-cpg-mssr # R-Car H239 - renesas,r8a7791-cpg-mssr # R-Car M2-W40 - renesas,r8a7792-cpg-mssr # R-Car V2H41 - renesas,r8a7793-cpg-mssr # R-Car M2-N42 - renesas,r8a7794-cpg-mssr # R-Car E243 - renesas,r8a7795-cpg-mssr # R-Car H344 - renesas,r8a7796-cpg-mssr # R-Car M3-W45 - renesas,r8a77961-cpg-mssr # R-Car M3-W+46 - renesas,r8a77965-cpg-mssr # R-Car M3-N47 - renesas,r8a77970-cpg-mssr # R-Car V3M48 - renesas,r8a77980-cpg-mssr # R-Car V3H49 - renesas,r8a77990-cpg-mssr # R-Car E350 - renesas,r8a77995-cpg-mssr # R-Car D351 - renesas,r8a779a0-cpg-mssr # R-Car V3U52 - renesas,r8a779f0-cpg-mssr # R-Car S4-853 - renesas,r8a779g0-cpg-mssr # R-Car V4H54 - renesas,r8a779h0-cpg-mssr # R-Car V4M55 56 reg:57 maxItems: 158 59 clocks:60 minItems: 161 maxItems: 262 63 clock-names:64 minItems: 165 maxItems: 266 items:67 enum:68 - extal # All69 - extalr # Most R-Car Gen3 and RZ/G270 - usb_extal # Most R-Car Gen2 and RZ/G171 72 '#clock-cells':73 description: |74 - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"75 and a core clock reference, as defined in76 <dt-bindings/clock/*-cpg-mssr.h>77 - For module clocks, the two clock specifier cells must be "CPG_MOD" and78 a module number, as defined in the datasheet.79 const: 280 81 '#power-domain-cells':82 description:83 SoC devices that are part of the CPG/MSSR Clock Domain and can be84 power-managed through Module Standby should refer to the CPG device node85 in their "power-domains" property, as documented by the generic PM Domain86 bindings in Documentation/devicetree/bindings/power/power-domain.yaml.87 const: 088 89 '#reset-cells':90 description:91 The single reset specifier cell must be the module number, as defined in92 the datasheet.93 const: 194 95if:96 not:97 properties:98 compatible:99 items:100 enum:101 - renesas,r7s9210-cpg-mssr102then:103 required:104 - '#reset-cells'105 106required:107 - compatible108 - reg109 - clocks110 - clock-names111 - '#clock-cells'112 - '#power-domain-cells'113 114additionalProperties: false115 116examples:117 - |118 cpg: clock-controller@e6150000 {119 compatible = "renesas,r8a7795-cpg-mssr";120 reg = <0xe6150000 0x1000>;121 clocks = <&extal_clk>, <&extalr_clk>;122 clock-names = "extal", "extalr";123 #clock-cells = <2>;124 #power-domain-cells = <0>;125 #reset-cells = <1>;126 };127