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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/renesas,cpg-mstp-clocks.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Renesas Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks8 9maintainers:10 - Geert Uytterhoeven <geert+renesas@glider.be>11 12description:13 The Clock Pulse Generator (CPG) can gate SoC device clocks. The gates are14 organized in groups of up to 32 gates.15 16 This device tree binding describes a single 32 gate clocks group per node.17 Clocks are referenced by user nodes by the Module Stop (MSTP) node phandle18 and the clock index in the group, from 0 to 31.19 20properties:21 compatible:22 items:23 - enum:24 - renesas,r7s72100-mstp-clocks # RZ/A125 - renesas,r8a73a4-mstp-clocks # R-Mobile APE626 - renesas,r8a7740-mstp-clocks # R-Mobile A127 - renesas,r8a7778-mstp-clocks # R-Car M128 - renesas,r8a7779-mstp-clocks # R-Car H129 - renesas,sh73a0-mstp-clocks # SH-Mobile AG530 - const: renesas,cpg-mstp-clocks31 32 reg:33 minItems: 134 items:35 - description: Module Stop Control Register (MSTPCR)36 - description: Module Stop Status Register (MSTPSR)37 38 clocks:39 minItems: 140 maxItems: 3241 42 '#clock-cells':43 const: 144 45 clock-indices:46 minItems: 147 maxItems: 3248 49 clock-output-names:50 minItems: 151 maxItems: 3252 53required:54 - compatible55 - reg56 - clocks57 - '#clock-cells'58 - clock-indices59 - clock-output-names60 61additionalProperties: false62 63examples:64 - |65 #include <dt-bindings/clock/r8a73a4-clock.h>66 mstp2_clks: mstp2_clks@e6150138 {67 compatible = "renesas,r8a73a4-mstp-clocks",68 "renesas,cpg-mstp-clocks";69 reg = <0xe6150138 4>, <0xe6150040 4>;70 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,71 <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;72 #clock-cells = <1>;73 clock-indices = <74 R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA175 R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB176 R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB377 R8A73A4_CLK_DMAC78 >;79 clock-output-names =80 "scifa0", "scifa1", "scifb0", "scifb1", "scifb2", "scifb3",81 "dmac";82 };83