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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/renesas,emev2-smu.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Renesas EMMA Mobile EV2 System Management Unit8 9maintainers:10 - Geert Uytterhoeven <geert+renesas@glider.be>11 - Magnus Damm <magnus.damm@gmail.com>12 13description: |14 The System Management Unit is described in user's manual R19UH0037EJ1000_SMU.15 This is not a clock provider, but clocks under SMU depend on it.16 17properties:18 compatible:19 const: renesas,emev2-smu20 21 reg:22 maxItems: 123 24 '#address-cells':25 const: 226 27 '#size-cells':28 const: 029 30required:31 - compatible32 - reg33 - '#address-cells'34 - '#size-cells'35 36patternProperties:37 ".*sclkdiv@.*":38 type: object39 40 description: |41 Function block with an input mux and a divider, which corresponds to42 "Serial clock generator" in fig. "Clock System Overview" of the manual,43 and "xxx frequency division setting register" (XXXCLKDIV) registers.44 This makes internal (neither input nor output) clock that is provided45 to input of xxxGCLK block.46 47 properties:48 compatible:49 const: renesas,emev2-smu-clkdiv50 51 reg:52 maxItems: 153 description:54 Byte offset from SMU base and Bit position in the register.55 56 clocks:57 minItems: 158 maxItems: 459 60 '#clock-cells':61 const: 062 63 required:64 - compatible65 - reg66 - clocks67 - '#clock-cells'68 69 additionalProperties: false70 71 ".*sclk@.*":72 type: object73 74 description: |75 Clock gating node shown as "Clock stop processing block" in the76 fig. "Clock System Overview" of the manual.77 Registers are "xxx clock gate control register" (XXXGCLKCTRL).78 79 properties:80 compatible:81 const: renesas,emev2-smu-gclk82 83 reg:84 maxItems: 185 description:86 Byte offset from SMU base and Bit position in the register.87 88 clocks:89 maxItems: 190 91 '#clock-cells':92 const: 093 94 required:95 - compatible96 - reg97 - clocks98 - '#clock-cells'99 100 additionalProperties: false101 102additionalProperties: true103 104examples:105 - |106 // Example of clock-tree description:107 //108 // This describes a clock path in the clock tree109 // c32ki -> pll3_fo -> usia_u0_sclkdiv -> usia_u0_sclk110 clocks@e0110000 {111 compatible = "renesas,emev2-smu";112 reg = <0xe0110000 0x10000>;113 #address-cells = <2>;114 #size-cells = <0>;115 116 c32ki: c32ki {117 compatible = "fixed-clock";118 clock-frequency = <32768>;119 #clock-cells = <0>;120 };121 pll3_fo: pll3_fo {122 compatible = "fixed-factor-clock";123 clocks = <&c32ki>;124 clock-div = <1>;125 clock-mult = <7000>;126 #clock-cells = <0>;127 };128 usia_u0_sclkdiv: usia_u0_sclkdiv@610,0 {129 compatible = "renesas,emev2-smu-clkdiv";130 reg = <0x610 0>;131 clocks = <&pll3_fo>;132 #clock-cells = <0>;133 };134 usia_u0_sclk: usia_u0_sclk@4a0,1 {135 compatible = "renesas,emev2-smu-gclk";136 reg = <0x4a0 1>;137 clocks = <&usia_u0_sclkdiv>;138 #clock-cells = <0>;139 };140 };141