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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Renesas RZ/{G2L,V2L,V2M} Clock Pulse Generator / Module Standby Mode8 9maintainers:10 - Geert Uytterhoeven <geert+renesas@glider.be>11 12description: |13 On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module14 Standby Mode share the same register block. On RZ/V2M, the functionality is15 similar, but does not have Clock Monitor Registers.16 17 They provide the following functionalities:18 - The CPG block generates various core clocks,19 - The Module Standby Mode block provides two functions:20 1. Module Standby, providing a Clock Domain to control the clock supply21 to individual SoC devices,22 2. Reset Control, to perform a software reset of individual SoC devices.23 24properties:25 compatible:26 enum:27 - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2} and RZ/Five28 - renesas,r9a07g044-cpg # RZ/G2{L,LC}29 - renesas,r9a07g054-cpg # RZ/V2L30 - renesas,r9a08g045-cpg # RZ/G3S31 - renesas,r9a09g011-cpg # RZ/V2M32 33 reg:34 maxItems: 135 36 clocks:37 maxItems: 138 39 clock-names:40 description:41 Clock source to CPG can be either from external clock input (EXCLK) or42 crystal oscillator (XIN/XOUT).43 const: extal44 45 '#clock-cells':46 description: |47 - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"48 and a core clock reference, as defined in49 <dt-bindings/clock/r9a0*-cpg.h>,50 - For module clocks, the two clock specifier cells must be "CPG_MOD" and51 a module number, as defined in <dt-bindings/clock/r9a0*-cpg.h>.52 const: 253 54 '#power-domain-cells':55 description:56 SoC devices that are part of the CPG/Module Standby Mode Clock Domain and57 can be power-managed through Module Standby should refer to the CPG device58 node in their "power-domains" property, as documented by the generic PM59 Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.60 The power domain specifiers defined in <dt-bindings/clock/r9a0*-cpg.h> could61 be used to reference individual CPG power domains.62 63 '#reset-cells':64 description:65 The single reset specifier cell must be the reset number, as defined in66 <dt-bindings/clock/r9a0*-cpg.h>.67 const: 168 69required:70 - compatible71 - reg72 - clocks73 - clock-names74 - '#clock-cells'75 - '#power-domain-cells'76 - '#reset-cells'77 78additionalProperties: false79 80allOf:81 - if:82 properties:83 compatible:84 contains:85 const: renesas,r9a08g045-cpg86 then:87 properties:88 '#power-domain-cells':89 const: 190 else:91 properties:92 '#power-domain-cells':93 const: 094 95examples:96 - |97 cpg: clock-controller@11010000 {98 compatible = "renesas,r9a07g044-cpg";99 reg = <0x11010000 0x10000>;100 clocks = <&extal_clk>;101 clock-names = "extal";102 #clock-cells = <2>;103 #power-domain-cells = <0>;104 #reset-cells = <1>;105 };106