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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)8 9maintainers:10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>11 12description:13 On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation14 and control of clock signals for the IP modules, generation and control of resets,15 and control over booting, low power consumption and power supply domains.16 17properties:18 compatible:19 const: renesas,r9a09g057-cpg20 21 reg:22 maxItems: 123 24 clocks:25 items:26 - description: AUDIO_EXTAL clock input27 - description: RTXIN clock input28 - description: QEXTAL clock input29 30 clock-names:31 items:32 - const: audio_extal33 - const: rtxin34 - const: qextal35 36 '#clock-cells':37 description: |38 - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"39 and a core clock reference, as defined in40 <dt-bindings/clock/renesas,r9a09g057-cpg.h>,41 - For module clocks, the two clock specifier cells must be "CPG_MOD" and42 a module number. The module number is calculated as the CLKON register43 offset index multiplied by 16, plus the actual bit in the register44 used to turn the CLK ON. For example, for CGC_GIC_0_GICCLK, the45 calculation is (1 * 16 + 3) = 0x13.46 const: 247 48 '#power-domain-cells':49 const: 050 51 '#reset-cells':52 description:53 The single reset specifier cell must be the reset number. The reset number54 is calculated as the reset register offset index multiplied by 16, plus the55 actual bit in the register used to reset the specific IP block. For example,56 for SYS_0_PRESETN, the calculation is (3 * 16 + 0) = 0x30.57 const: 158 59required:60 - compatible61 - reg62 - clocks63 - clock-names64 - '#clock-cells'65 - '#power-domain-cells'66 - '#reset-cells'67 68additionalProperties: false69 70examples:71 - |72 clock-controller@10420000 {73 compatible = "renesas,r9a09g057-cpg";74 reg = <0x10420000 0x10000>;75 clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;76 clock-names = "audio_extal", "rtxin", "qextal";77 #clock-cells = <2>;78 #power-domain-cells = <0>;79 #reset-cells = <1>;80 };81