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1# SPDX-License-Identifier: (GPL-2.0+ OR MIT)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/rockchip,rk3128-cru.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Rockchip RK3126/RK3128 Clock and Reset Unit (CRU)8 9maintainers:10 - Elaine Zhang <zhangqing@rock-chips.com>11 - Heiko Stuebner <heiko@sntech.de>12 13description: |14 The RK3126/RK3128 clock controller generates and supplies clock to various15 controllers within the SoC and also implements a reset controller for SoC16 peripherals.17 Each clock is assigned an identifier and client nodes can use this identifier18 to specify the clock which they consume. All available clocks are defined as19 preprocessor macros in the dt-bindings/clock/rk3128-cru.h headers and can be20 used in device tree sources. Similar macros exist for the reset sources in21 these files.22 23properties:24 compatible:25 enum:26 - rockchip,rk3126-cru27 - rockchip,rk3128-cru28 29 reg:30 maxItems: 131 32 "#clock-cells":33 const: 134 35 "#reset-cells":36 const: 137 38 clocks:39 minItems: 140 maxItems: 341 42 clock-names:43 minItems: 144 items:45 - const: xin24m46 - enum:47 - ext_i2s48 - gmac_clkin49 - enum:50 - ext_i2s51 - gmac_clkin52 53 rockchip,grf:54 $ref: /schemas/types.yaml#/definitions/phandle55 description:56 Phandle to the syscon managing the "general register files" (GRF),57 if missing pll rates are not changeable, due to the missing pll58 lock status.59 60required:61 - compatible62 - reg63 - "#clock-cells"64 - "#reset-cells"65 66additionalProperties: false67 68examples:69 - |70 cru: clock-controller@20000000 {71 compatible = "rockchip,rk3128-cru";72 reg = <0x20000000 0x1000>;73 rockchip,grf = <&grf>;74 #clock-cells = <1>;75 #reset-cells = <1>;76 };77