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1* Rockchip RK3328 Clock and Reset Unit2 3The RK3328 clock controller generates and supplies clock to various4controllers within the SoC and also implements a reset controller for SoC5peripherals.6 7Required Properties:8 9- compatible: should be "rockchip,rk3328-cru"10- reg: physical base address of the controller and length of memory mapped11 region.12- #clock-cells: should be 1.13- #reset-cells: should be 1.14 15Optional Properties:16 17- rockchip,grf: phandle to the syscon managing the "general register files"18 If missing pll rates are not changeable, due to the missing pll lock status.19 20Each clock is assigned an identifier and client nodes can use this identifier21to specify the clock which they consume. All available clocks are defined as22preprocessor macros in the dt-bindings/clock/rk3328-cru.h headers and can be23used in device tree sources. Similar macros exist for the reset sources in24these files.25 26External clocks:27 28There are several clocks that are generated outside the SoC. It is expected29that they are defined using standard clock bindings with following30clock-output-names:31 - "xin24m" - crystal input - required,32 - "clkin_i2s" - external I2S clock - optional,33 - "gmac_clkin" - external GMAC clock - optional34 - "phy_50m_out" - output clock of the pll in the mac phy35 - "hdmi_phy" - output clock of the hdmi phy pll - optional36 37Example: Clock controller node:38 39 cru: clock-controller@ff440000 {40 compatible = "rockchip,rk3328-cru";41 reg = <0x0 0xff440000 0x0 0x1000>;42 rockchip,grf = <&grf>;43 44 #clock-cells = <1>;45 #reset-cells = <1>;46 };47 48Example: UART controller node that consumes the clock generated by the clock49 controller:50 51 uart0: serial@ff120000 {52 compatible = "snps,dw-apb-uart";53 reg = <0xff120000 0x100>;54 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;55 reg-shift = <2>;56 reg-io-width = <4>;57 clocks = <&cru SCLK_UART0>;58 };59