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1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/rockchip,rk3568-cru.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: ROCKCHIP rk3568 Family Clock Control Module8 9maintainers:10 - Elaine Zhang <zhangqing@rock-chips.com>11 - Heiko Stuebner <heiko@sntech.de>12 13description: |14 The RK3568 clock controller generates the clock and also implements a15 reset controller for SoC peripherals.16 (examples: provide SCLK_UART1\PCLK_UART1 and SRST_P_UART1\SRST_S_UART1 for UART module)17 Each clock is assigned an identifier and client nodes can use this identifier18 to specify the clock which they consume. All available clocks are defined as19 preprocessor macros in the dt-bindings/clock/rk3568-cru.h headers and can be20 used in device tree sources.21 22properties:23 compatible:24 enum:25 - rockchip,rk3568-cru26 - rockchip,rk3568-pmucru27 28 reg:29 maxItems: 130 31 "#clock-cells":32 const: 133 34 "#reset-cells":35 const: 136 37 clocks:38 maxItems: 139 40 clock-names:41 const: xin24m42 43 rockchip,grf:44 $ref: /schemas/types.yaml#/definitions/phandle45 description:46 Phandle to the syscon managing the "general register files" (GRF),47 if missing pll rates are not changeable, due to the missing pll48 lock status.49 50required:51 - compatible52 - reg53 - "#clock-cells"54 - "#reset-cells"55 56additionalProperties: false57 58examples:59 # Clock Control Module node:60 - |61 pmucru: clock-controller@fdd00000 {62 compatible = "rockchip,rk3568-pmucru";63 reg = <0xfdd00000 0x1000>;64 #clock-cells = <1>;65 #reset-cells = <1>;66 };67 - |68 cru: clock-controller@fdd20000 {69 compatible = "rockchip,rk3568-cru";70 reg = <0xfdd20000 0x1000>;71 #clock-cells = <1>;72 #reset-cells = <1>;73 };74