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1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/rockchip,rk3588-cru.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Rockchip rk3588 Family Clock and Reset Control Module8 9maintainers:10 - Elaine Zhang <zhangqing@rock-chips.com>11 - Heiko Stuebner <heiko@sntech.de>12 13description: |14 The RK3588 clock controller generates the clock and also implements a reset15 controller for SoC peripherals. For example it provides SCLK_UART2 and16 PCLK_UART2, as well as SRST_P_UART2 and SRST_S_UART2 for the second UART17 module.18 Each clock is assigned an identifier and client nodes can use this identifier19 to specify the clock which they consume. All available clock and reset IDs20 are defined as preprocessor macros in dt-binding headers.21 22properties:23 compatible:24 enum:25 - rockchip,rk3588-cru26 27 reg:28 maxItems: 129 30 "#clock-cells":31 const: 132 33 "#reset-cells":34 const: 135 36 clocks:37 minItems: 238 maxItems: 239 40 clock-names:41 items:42 - const: xin24m43 - const: xin32k44 45 rockchip,grf:46 $ref: /schemas/types.yaml#/definitions/phandle47 description: >48 phandle to the syscon managing the "general register files". It is used49 for GRF muxes, if missing any muxes present in the GRF will not be50 available.51 52required:53 - compatible54 - reg55 - "#clock-cells"56 - "#reset-cells"57 58additionalProperties: false59 60examples:61 - |62 cru: clock-controller@fd7c0000 {63 compatible = "rockchip,rk3588-cru";64 reg = <0xfd7c0000 0x5c000>;65 #clock-cells = <1>;66 #reset-cells = <1>;67 };68