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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/samsung,exynos850-clock.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Samsung Exynos850 SoC clock controller8 9maintainers:10 - Sam Protsenko <semen.protsenko@linaro.org>11 - Chanwoo Choi <cw00.choi@samsung.com>12 - Krzysztof Kozlowski <krzk@kernel.org>13 - Sylwester Nawrocki <s.nawrocki@samsung.com>14 - Tomasz Figa <tomasz.figa@gmail.com>15 16description: |17 Exynos850 clock controller is comprised of several CMU units, generating18 clocks for different domains. Those CMU units are modeled as separate device19 tree nodes, and might depend on each other. Root clocks in that clock tree are20 two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external21 clocks must be defined as fixed-rate clocks in dts.22 23 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and24 dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.25 26 Each clock is assigned an identifier and client nodes can use this identifier27 to specify the clock which they consume. All clocks available for usage28 in clock consumer nodes are defined as preprocessor macros in29 'dt-bindings/clock/exynos850.h' header.30 31properties:32 compatible:33 enum:34 - samsung,exynos850-cmu-top35 - samsung,exynos850-cmu-apm36 - samsung,exynos850-cmu-aud37 - samsung,exynos850-cmu-cmgp38 - samsung,exynos850-cmu-core39 - samsung,exynos850-cmu-cpucl040 - samsung,exynos850-cmu-cpucl141 - samsung,exynos850-cmu-dpu42 - samsung,exynos850-cmu-g3d43 - samsung,exynos850-cmu-hsi44 - samsung,exynos850-cmu-is45 - samsung,exynos850-cmu-mfcmscl46 - samsung,exynos850-cmu-peri47 48 clocks:49 minItems: 150 maxItems: 551 52 clock-names:53 minItems: 154 maxItems: 555 56 "#clock-cells":57 const: 158 59 reg:60 maxItems: 161 62allOf:63 - if:64 properties:65 compatible:66 contains:67 const: samsung,exynos850-cmu-top68 69 then:70 properties:71 clocks:72 items:73 - description: External reference clock (26 MHz)74 75 clock-names:76 items:77 - const: oscclk78 79 - if:80 properties:81 compatible:82 contains:83 const: samsung,exynos850-cmu-apm84 85 then:86 properties:87 clocks:88 items:89 - description: External reference clock (26 MHz)90 - description: CMU_APM bus clock (from CMU_TOP)91 92 clock-names:93 items:94 - const: oscclk95 - const: dout_clkcmu_apm_bus96 97 - if:98 properties:99 compatible:100 contains:101 const: samsung,exynos850-cmu-aud102 103 then:104 properties:105 clocks:106 items:107 - description: External reference clock (26 MHz)108 - description: AUD clock (from CMU_TOP)109 110 clock-names:111 items:112 - const: oscclk113 - const: dout_aud114 115 - if:116 properties:117 compatible:118 contains:119 const: samsung,exynos850-cmu-cmgp120 121 then:122 properties:123 clocks:124 items:125 - description: External reference clock (26 MHz)126 - description: CMU_CMGP bus clock (from CMU_APM)127 128 clock-names:129 items:130 - const: oscclk131 - const: gout_clkcmu_cmgp_bus132 133 - if:134 properties:135 compatible:136 contains:137 const: samsung,exynos850-cmu-core138 139 then:140 properties:141 clocks:142 items:143 - description: External reference clock (26 MHz)144 - description: CMU_CORE bus clock (from CMU_TOP)145 - description: CCI clock (from CMU_TOP)146 - description: eMMC clock (from CMU_TOP)147 - description: SSS clock (from CMU_TOP)148 149 clock-names:150 items:151 - const: oscclk152 - const: dout_core_bus153 - const: dout_core_cci154 - const: dout_core_mmc_embd155 - const: dout_core_sss156 157 - if:158 properties:159 compatible:160 contains:161 const: samsung,exynos850-cmu-cpucl0162 163 then:164 properties:165 clocks:166 items:167 - description: External reference clock (26 MHz)168 - description: CPUCL0 switch clock (from CMU_TOP)169 - description: CPUCL0 debug clock (from CMU_TOP)170 171 clock-names:172 items:173 - const: oscclk174 - const: dout_cpucl0_switch175 - const: dout_cpucl0_dbg176 177 - if:178 properties:179 compatible:180 contains:181 const: samsung,exynos850-cmu-cpucl1182 183 then:184 properties:185 clocks:186 items:187 - description: External reference clock (26 MHz)188 - description: CPUCL1 switch clock (from CMU_TOP)189 - description: CPUCL1 debug clock (from CMU_TOP)190 191 clock-names:192 items:193 - const: oscclk194 - const: dout_cpucl1_switch195 - const: dout_cpucl1_dbg196 197 - if:198 properties:199 compatible:200 contains:201 const: samsung,exynos850-cmu-dpu202 203 then:204 properties:205 clocks:206 items:207 - description: External reference clock (26 MHz)208 - description: DPU clock (from CMU_TOP)209 210 clock-names:211 items:212 - const: oscclk213 - const: dout_dpu214 215 - if:216 properties:217 compatible:218 contains:219 const: samsung,exynos850-cmu-g3d220 221 then:222 properties:223 clocks:224 items:225 - description: External reference clock (26 MHz)226 - description: G3D clock (from CMU_TOP)227 228 clock-names:229 items:230 - const: oscclk231 - const: dout_g3d_switch232 233 - if:234 properties:235 compatible:236 contains:237 const: samsung,exynos850-cmu-hsi238 239 then:240 properties:241 clocks:242 items:243 - description: External reference clock (26 MHz)244 - description: External RTC clock (32768 Hz)245 - description: CMU_HSI bus clock (from CMU_TOP)246 - description: SD card clock (from CMU_TOP)247 - description: USB 2.0 DRD clock (from CMU_TOP)248 249 clock-names:250 items:251 - const: oscclk252 - const: rtcclk253 - const: dout_hsi_bus254 - const: dout_hsi_mmc_card255 - const: dout_hsi_usb20drd256 257 - if:258 properties:259 compatible:260 contains:261 const: samsung,exynos850-cmu-is262 263 then:264 properties:265 clocks:266 items:267 - description: External reference clock (26 MHz)268 - description: CMU_IS bus clock (from CMU_TOP)269 - description: Image Texture Processing core clock (from CMU_TOP)270 - description: Visual Recognition Accelerator clock (from CMU_TOP)271 - description: Geometric Distortion Correction clock (from CMU_TOP)272 273 clock-names:274 items:275 - const: oscclk276 - const: dout_is_bus277 - const: dout_is_itp278 - const: dout_is_vra279 - const: dout_is_gdc280 281 - if:282 properties:283 compatible:284 contains:285 const: samsung,exynos850-cmu-mfcmscl286 287 then:288 properties:289 clocks:290 items:291 - description: External reference clock (26 MHz)292 - description: Multi-Format Codec clock (from CMU_TOP)293 - description: Memory to Memory Scaler clock (from CMU_TOP)294 - description: Multi-Channel Scaler clock (from CMU_TOP)295 - description: JPEG codec clock (from CMU_TOP)296 297 clock-names:298 items:299 - const: oscclk300 - const: dout_mfcmscl_mfc301 - const: dout_mfcmscl_m2m302 - const: dout_mfcmscl_mcsc303 - const: dout_mfcmscl_jpeg304 305 - if:306 properties:307 compatible:308 contains:309 const: samsung,exynos850-cmu-peri310 311 then:312 properties:313 clocks:314 items:315 - description: External reference clock (26 MHz)316 - description: CMU_PERI bus clock (from CMU_TOP)317 - description: UART clock (from CMU_TOP)318 - description: Parent clock for HSI2C and SPI (from CMU_TOP)319 320 clock-names:321 items:322 - const: oscclk323 - const: dout_peri_bus324 - const: dout_peri_uart325 - const: dout_peri_ip326 327required:328 - compatible329 - "#clock-cells"330 - clocks331 - clock-names332 - reg333 334additionalProperties: false335 336examples:337 # Clock controller node for CMU_PERI338 - |339 #include <dt-bindings/clock/exynos850.h>340 341 cmu_peri: clock-controller@10030000 {342 compatible = "samsung,exynos850-cmu-peri";343 reg = <0x10030000 0x8000>;344 #clock-cells = <1>;345 346 clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>,347 <&cmu_top CLK_DOUT_PERI_UART>,348 <&cmu_top CLK_DOUT_PERI_IP>;349 clock-names = "oscclk", "dout_peri_bus",350 "dout_peri_uart", "dout_peri_ip";351 };352 353...354