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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/samsung,exynosautov9-clock.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Samsung Exynos Auto v9 SoC clock controller8 9maintainers:10 - Chanho Park <chanho61.park@samsung.com>11 - Chanwoo Choi <cw00.choi@samsung.com>12 - Krzysztof Kozlowski <krzk@kernel.org>13 - Sylwester Nawrocki <s.nawrocki@samsung.com>14 - Tomasz Figa <tomasz.figa@gmail.com>15 16description: |17 Exynos Auto v9 clock controller is comprised of several CMU units, generating18 clocks for different domains. Those CMU units are modeled as separate device19 tree nodes, and might depend on each other. Root clocks in that clock tree are20 two external clocks:: OSCCLK/XTCXO (26 MHz) and RTCCLK/XrtcXTI (32768 Hz).21 The external OSCCLK must be defined as fixed-rate clock in dts.22 23 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and24 dividers; all other clocks of function blocks (other CMUs) are usually25 derived from CMU_TOP.26 27 Each clock is assigned an identifier and client nodes can use this identifier28 to specify the clock which they consume. All clocks available for usage29 in clock consumer nodes are defined as preprocessor macros in30 'include/dt-bindings/clock/samsung,exynosautov9.h' header.31 32properties:33 compatible:34 enum:35 - samsung,exynosautov9-cmu-top36 - samsung,exynosautov9-cmu-busmc37 - samsung,exynosautov9-cmu-core38 - samsung,exynosautov9-cmu-dpum39 - samsung,exynosautov9-cmu-fsys040 - samsung,exynosautov9-cmu-fsys141 - samsung,exynosautov9-cmu-fsys242 - samsung,exynosautov9-cmu-peric043 - samsung,exynosautov9-cmu-peric144 - samsung,exynosautov9-cmu-peris45 46 clocks:47 minItems: 148 maxItems: 549 50 clock-names:51 minItems: 152 maxItems: 553 54 "#clock-cells":55 const: 156 57 reg:58 maxItems: 159 60allOf:61 - if:62 properties:63 compatible:64 contains:65 const: samsung,exynosautov9-cmu-top66 67 then:68 properties:69 clocks:70 items:71 - description: External reference clock (26 MHz)72 73 clock-names:74 items:75 - const: oscclk76 77 - if:78 properties:79 compatible:80 contains:81 const: samsung,exynosautov9-cmu-busmc82 83 then:84 properties:85 clocks:86 items:87 - description: External reference clock (26 MHz)88 - description: CMU_BUSMC bus clock (from CMU_TOP)89 90 clock-names:91 items:92 - const: oscclk93 - const: dout_clkcmu_busmc_bus94 95 - if:96 properties:97 compatible:98 contains:99 const: samsung,exynosautov9-cmu-core100 101 then:102 properties:103 clocks:104 items:105 - description: External reference clock (26 MHz)106 - description: CMU_CORE bus clock (from CMU_TOP)107 108 clock-names:109 items:110 - const: oscclk111 - const: dout_clkcmu_core_bus112 113 - if:114 properties:115 compatible:116 contains:117 const: samsung,exynosautov9-cmu-dpum118 119 then:120 properties:121 clocks:122 items:123 - description: External reference clock (26 MHz)124 - description: DPU Main bus clock (from CMU_TOP)125 126 clock-names:127 items:128 - const: oscclk129 - const: bus130 131 - if:132 properties:133 compatible:134 contains:135 const: samsung,exynosautov9-cmu-fsys0136 137 then:138 properties:139 clocks:140 items:141 - description: External reference clock (26 MHz)142 - description: CMU_FSYS0 bus clock (from CMU_TOP)143 - description: CMU_FSYS0 pcie clock (from CMU_TOP)144 145 clock-names:146 items:147 - const: oscclk148 - const: dout_clkcmu_fsys0_bus149 - const: dout_clkcmu_fsys0_pcie150 151 - if:152 properties:153 compatible:154 contains:155 const: samsung,exynosautov9-cmu-fsys1156 157 then:158 properties:159 clocks:160 items:161 - description: External reference clock (26 MHz)162 - description: CMU_FSYS1 bus clock (from CMU_TOP)163 - description: CMU_FSYS1 mmc card clock (from CMU_TOP)164 - description: CMU_FSYS1 usb clock (from CMU_TOP)165 166 clock-names:167 items:168 - const: oscclk169 - const: dout_clkcmu_fsys1_bus170 - const: gout_clkcmu_fsys1_mmc_card171 - const: dout_clkcmu_fsys1_usbdrd172 173 - if:174 properties:175 compatible:176 contains:177 const: samsung,exynosautov9-cmu-fsys2178 179 then:180 properties:181 clocks:182 items:183 - description: External reference clock (26 MHz)184 - description: CMU_FSYS2 bus clock (from CMU_TOP)185 - description: UFS clock (from CMU_TOP)186 - description: Ethernet clock (from CMU_TOP)187 188 clock-names:189 items:190 - const: oscclk191 - const: dout_clkcmu_fsys2_bus192 - const: dout_fsys2_clkcmu_ufs_embd193 - const: dout_fsys2_clkcmu_ethernet194 195 - if:196 properties:197 compatible:198 contains:199 const: samsung,exynosautov9-cmu-peric0200 201 then:202 properties:203 clocks:204 items:205 - description: External reference clock (26 MHz)206 - description: CMU_PERIC0 bus clock (from CMU_TOP)207 - description: PERIC0 IP clock (from CMU_TOP)208 209 clock-names:210 items:211 - const: oscclk212 - const: dout_clkcmu_peric0_bus213 - const: dout_clkcmu_peric0_ip214 215 - if:216 properties:217 compatible:218 contains:219 const: samsung,exynosautov9-cmu-peric1220 221 then:222 properties:223 clocks:224 items:225 - description: External reference clock (26 MHz)226 - description: CMU_PERIC1 bus clock (from CMU_TOP)227 - description: PERIC1 IP clock (from CMU_TOP)228 229 clock-names:230 items:231 - const: oscclk232 - const: dout_clkcmu_peric1_bus233 - const: dout_clkcmu_peric1_ip234 235 - if:236 properties:237 compatible:238 contains:239 const: samsung,exynosautov9-cmu-peris240 241 then:242 properties:243 clocks:244 items:245 - description: External reference clock (26 MHz)246 - description: CMU_PERIS bus clock (from CMU_TOP)247 248 clock-names:249 items:250 - const: oscclk251 - const: dout_clkcmu_peris_bus252 253required:254 - compatible255 - "#clock-cells"256 - clocks257 - clock-names258 - reg259 260additionalProperties: false261 262examples:263 # Clock controller node for CMU_FSYS2264 - |265 #include <dt-bindings/clock/samsung,exynosautov9.h>266 267 cmu_fsys2: clock-controller@17c00000 {268 compatible = "samsung,exynosautov9-cmu-fsys2";269 reg = <0x17c00000 0x8000>;270 #clock-cells = <1>;271 272 clocks = <&xtcxo>,273 <&cmu_top DOUT_CLKCMU_FSYS2_BUS>,274 <&cmu_top DOUT_CLKCMU_FSYS2_UFS_EMBD>,275 <&cmu_top DOUT_CLKCMU_FSYS2_ETHERNET>;276 clock-names = "oscclk",277 "dout_clkcmu_fsys2_bus",278 "dout_fsys2_clkcmu_ufs_embd",279 "dout_fsys2_clkcmu_ethernet";280 };281 282...283