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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2# Copyright (C) 2020 SiFive, Inc.3%YAML 1.24---5$id: http://devicetree.org/schemas/clock/sifive/fu740-prci.yaml#6$schema: http://devicetree.org/meta-schemas/core.yaml#7 8title: SiFive FU740 Power Reset Clock Interrupt Controller (PRCI)9 10maintainers:11 - Zong Li <zong.li@sifive.com>12 - Paul Walmsley <paul.walmsley@sifive.com>13 14description:15 On the FU740 family of SoCs, most system-wide clock and reset integration16 is via the PRCI IP block.17 The clock consumer should specify the desired clock via the clock ID18 macros defined in include/dt-bindings/clock/sifive-fu740-prci.h.19 These macros begin with PRCI_CLK_.20 21 The hfclk and rtcclk nodes are required, and represent physical22 crystals or resonators located on the PCB. These nodes should be present23 underneath /, rather than /soc.24 25properties:26 compatible:27 const: sifive,fu740-c000-prci28 29 reg:30 maxItems: 131 32 clocks:33 items:34 - description: high frequency clock.35 - description: RTL clock.36 37 clock-names:38 items:39 - const: hfclk40 - const: rtcclk41 42 "#clock-cells":43 const: 144 45 "#reset-cells":46 const: 147 48required:49 - compatible50 - reg51 - clocks52 - "#clock-cells"53 54additionalProperties: false55 56examples:57 - |58 prci: clock-controller@10000000 {59 compatible = "sifive,fu740-c000-prci";60 reg = <0x10000000 0x1000>;61 clocks = <&hfclk>, <&rtcclk>;62 #clock-cells = <1>;63 #reset-cells = <1>;64 };65