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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/silabs,si5351.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Silicon Labs Si5351A/B/C programmable I2C clock generators8 9description: |10 The Silicon Labs Si5351A/B/C are programmable I2C clock generators with up to11 8 outputs. Si5351A also has a reduced pin-count package (10-MSOP) where only 312 output clocks are accessible. The internal structure of the clock generators13 can be found in [1].14 15 [1] Si5351A/B/C Data Sheet16 https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf17 18maintainers:19 - Alvin Šipraga <alsi@bang-olufsen.dk>20 21properties:22 compatible:23 enum:24 - silabs,si5351a # Si5351A, 20-QFN package25 - silabs,si5351a-msop # Si5351A, 10-MSOP package26 - silabs,si5351b # Si5351B, 20-QFN package27 - silabs,si5351c # Si5351C, 20-QFN package28 29 reg:30 enum:31 - 0x6032 - 0x6133 34 "#address-cells":35 const: 136 37 "#size-cells":38 const: 039 40 "#clock-cells":41 const: 142 43 clocks:44 minItems: 145 maxItems: 246 47 clock-names:48 minItems: 149 items:50 - const: xtal51 - const: clkin52 53 silabs,pll-source:54 $ref: /schemas/types.yaml#/definitions/uint32-matrix55 description: |56 A list of cell pairs containing a PLL index and its source. Allows to57 overwrite clock source of the internal PLLs.58 items:59 items:60 - description: PLL A (0) or PLL B (1)61 enum: [ 0, 1 ]62 - description: PLL source, XTAL (0) or CLKIN (1, Si5351C only).63 enum: [ 0, 1 ]64 65 silabs,pll-reset-mode:66 $ref: /schemas/types.yaml#/definitions/uint32-matrix67 minItems: 168 maxItems: 269 description: A list of cell pairs containing a PLL index and its reset mode.70 items:71 items:72 - description: PLL A (0) or PLL B (1)73 enum: [ 0, 1 ]74 - description: |75 Reset mode for the PLL. Mode can be one of:76 77 0 - reset whenever PLL rate is adjusted (default mode)78 1 - do not reset when PLL rate is adjusted79 80 In mode 1, the PLL is only reset if the silabs,pll-reset is81 specified in one of the clock output child nodes that also sources82 the PLL. This mode may be preferable if output clocks are expected83 to be adjusted without glitches.84 enum: [ 0, 1 ]85 86patternProperties:87 "^clkout@[0-7]$":88 type: object89 90 additionalProperties: false91 92 properties:93 reg:94 description: Clock output number.95 96 clock-frequency: true97 98 silabs,clock-source:99 $ref: /schemas/types.yaml#/definitions/uint32100 description: |101 Source clock of the this output's divider stage.102 103 0 - use multisynth N for this output, where N is the output number104 1 - use either multisynth 0 (if output number is 0-3) or multisynth 4105 (otherwise) for this output106 2 - use XTAL for this output107 3 - use CLKIN for this output (Si5351C only)108 109 silabs,drive-strength:110 $ref: /schemas/types.yaml#/definitions/uint32111 enum: [ 2, 4, 6, 8 ]112 description: Output drive strength in mA.113 114 silabs,multisynth-source:115 $ref: /schemas/types.yaml#/definitions/uint32116 enum: [ 0, 1 ]117 description:118 Source PLL A (0) or B (1) for the corresponding multisynth divider.119 120 silabs,pll-master:121 type: boolean122 description: |123 The frequency of the source PLL is allowed to be changed by the124 multisynth when setting the rate of this clock output.125 126 silabs,pll-reset:127 type: boolean128 description: Reset the source PLL when enabling this clock output.129 130 silabs,disable-state:131 $ref: /schemas/types.yaml#/definitions/uint32132 enum: [ 0, 1, 2, 3 ]133 description: |134 Clock output disable state. The state can be one of:135 136 0 - clock output is driven LOW when disabled137 1 - clock output is driven HIGH when disabled138 2 - clock output is FLOATING (HIGH-Z) when disabled139 3 - clock output is never disabled140 141 allOf:142 - if:143 properties:144 compatible:145 contains:146 const: silabs,si5351a-msop147 then:148 properties:149 reg:150 maximum: 2151 else:152 properties:153 reg:154 maximum: 7155 156 - if:157 properties:158 compatible:159 contains:160 const: silabs,si5351c161 then:162 properties:163 silabs,clock-source:164 enum: [ 0, 1, 2, 3 ]165 else:166 properties:167 silabs,clock-source:168 enum: [ 0, 1, 2 ]169 170 required:171 - reg172 173allOf:174 - if:175 properties:176 compatible:177 contains:178 enum:179 - silabs,si5351a180 - silabs,si5351a-msop181 - silabs,si5351b182 then:183 properties:184 clocks:185 maxItems: 1186 clock-names:187 maxItems: 1188 189required:190 - reg191 - "#address-cells"192 - "#size-cells"193 - "#clock-cells"194 - clocks195 - clock-names196 197unevaluatedProperties: false198 199examples:200 - |201 i2c {202 #address-cells = <1>;203 #size-cells = <0>;204 205 clock-generator@60 {206 compatible = "silabs,si5351a-msop";207 reg = <0x60>;208 #address-cells = <1>;209 #size-cells = <0>;210 #clock-cells = <1>;211 212 /* Connect XTAL input to 25MHz reference */213 clocks = <&ref25>;214 clock-names = "xtal";215 216 /* Use XTAL input as source of PLL0 and PLL1 */217 silabs,pll-source = <0 0>, <1 0>;218 219 /* Don't reset PLL1 on rate adjustment */220 silabs,pll-reset-mode = <1 1>;221 222 /*223 * Overwrite CLK0 configuration with:224 * - 8 mA output drive strength225 * - PLL0 as clock source of multisynth 0226 * - Multisynth 0 as clock source of output divider227 * - Multisynth 0 can change PLL0228 * - Set initial clock frequency of 74.25MHz229 */230 clkout@0 {231 reg = <0>;232 silabs,drive-strength = <8>;233 silabs,multisynth-source = <0>;234 silabs,clock-source = <0>;235 silabs,pll-master;236 clock-frequency = <74250000>;237 };238 239 /*240 * Overwrite CLK1 configuration with:241 * - 4 mA output drive strength242 * - PLL1 as clock source of multisynth 1243 * - Multisynth 1 as clock source of output divider244 * - Multisynth 1 can change PLL1245 * - Reset PLL1 when enabling this clock output246 */247 clkout@1 {248 reg = <1>;249 silabs,drive-strength = <4>;250 silabs,multisynth-source = <1>;251 silabs,clock-source = <0>;252 silabs,pll-master;253 silabs,pll-reset;254 };255 256 /*257 * Overwrite CLK2 configuration with:258 * - XTAL as clock source of output divider259 */260 clkout@2 {261 reg = <2>;262 silabs,clock-source = <2>;263 };264 };265 };266