62 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/sophgo,sg2042-clkgen.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Sophgo SG2042 Clock Generator for divider/mux/gate8 9maintainers:10 - Chen Wang <unicorn_wang@outlook.com>11 12properties:13 compatible:14 const: sophgo,sg2042-clkgen15 16 reg:17 maxItems: 118 19 clocks:20 items:21 - description: Main PLL22 - description: Fixed PLL23 - description: DDR PLL 024 - description: DDR PLL 125 26 clock-names:27 items:28 - const: mpll29 - const: fpll30 - const: dpll031 - const: dpll132 33 '#clock-cells':34 const: 135 description:36 See <dt-bindings/clock/sophgo,sg2042-clkgen.h> for valid indices.37 38required:39 - compatible40 - reg41 - clocks42 - clock-names43 - '#clock-cells'44 45additionalProperties: false46 47examples:48 - |49 clock-controller@30012000 {50 compatible = "sophgo,sg2042-clkgen";51 reg = <0x30012000 0x1000>;52 clocks = <&pllclk 0>,53 <&pllclk 1>,54 <&pllclk 2>,55 <&pllclk 3>;56 clock-names = "mpll",57 "fpll",58 "dpll0",59 "dpll1";60 #clock-cells = <1>;61 };62