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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2# Copyright 2022 Unisoc Inc.3%YAML 1.24---5$id: http://devicetree.org/schemas/clock/sprd,ums512-clk.yaml#6$schema: http://devicetree.org/meta-schemas/core.yaml#7 8title: UMS512 Soc clock controller9 10maintainers:11 - Orson Zhai <orsonzhai@gmail.com>12 - Baolin Wang <baolin.wang7@gmail.com>13 - Chunyan Zhang <zhang.lyra@gmail.com>14 15properties:16 compatible:17 enum:18 - sprd,ums512-apahb-gate19 - sprd,ums512-ap-clk20 - sprd,ums512-aonapb-clk21 - sprd,ums512-pmu-gate22 - sprd,ums512-g0-pll23 - sprd,ums512-g2-pll24 - sprd,ums512-g3-pll25 - sprd,ums512-gc-pll26 - sprd,ums512-aon-gate27 - sprd,ums512-audcpapb-gate28 - sprd,ums512-audcpahb-gate29 - sprd,ums512-gpu-clk30 - sprd,ums512-mm-clk31 - sprd,ums512-mm-gate-clk32 - sprd,ums512-apapb-gate33 34 "#clock-cells":35 const: 136 37 clocks:38 minItems: 139 maxItems: 440 description: |41 The input parent clock(s) phandle for the clock, only list42 fixed clocks which are declared in devicetree.43 44 clock-names:45 minItems: 146 items:47 - const: ext-26m48 - const: ext-32k49 - const: ext-4m50 - const: rco-100m51 52 reg:53 maxItems: 154 55required:56 - compatible57 - '#clock-cells'58 - reg59 60additionalProperties: false61 62examples:63 - |64 ap_clk: clock-controller@20200000 {65 compatible = "sprd,ums512-ap-clk";66 reg = <0x20200000 0x1000>;67 clocks = <&ext_26m>;68 clock-names = "ext-26m";69 #clock-cells = <1>;70 };71...72