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1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: StarFive JH7110 PLL Clock Generator8 9description:10 These PLLs are high speed, low jitter frequency synthesizers in the JH7110.11 Each PLL works in integer mode or fraction mode, with configuration12 registers in the sys syscon. So the PLLs node should be a child of13 SYS-SYSCON node.14 The formula for calculating frequency is15 Fvco = Fref * (NI + NF) / M / Q116 17maintainers:18 - Xingyu Wu <xingyu.wu@starfivetech.com>19 20properties:21 compatible:22 const: starfive,jh7110-pll23 24 clocks:25 maxItems: 126 description: Main Oscillator (24 MHz)27 28 '#clock-cells':29 const: 130 description:31 See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.32 33required:34 - compatible35 - clocks36 - '#clock-cells'37 38additionalProperties: false39 40examples:41 - |42 clock-controller {43 compatible = "starfive,jh7110-pll";44 clocks = <&osc>;45 #clock-cells = <1>;46 };47