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1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/starfive,jh7110-stgcrg.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: StarFive JH7110 System-Top-Group Clock and Reset Generator8 9maintainers:10 - Xingyu Wu <xingyu.wu@starfivetech.com>11 12properties:13 compatible:14 const: starfive,jh7110-stgcrg15 16 reg:17 maxItems: 118 19 clocks:20 items:21 - description: Main Oscillator (24 MHz)22 - description: HIFI4 core23 - description: STG AXI/AHB24 - description: USB (125 MHz)25 - description: CPU Bus26 - description: HIFI4 Axi27 - description: NOC STG Bus28 - description: APB Bus29 30 clock-names:31 items:32 - const: osc33 - const: hifi4_core34 - const: stg_axiahb35 - const: usb_125m36 - const: cpu_bus37 - const: hifi4_axi38 - const: nocstg_bus39 - const: apb_bus40 41 '#clock-cells':42 const: 143 description:44 See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.45 46 '#reset-cells':47 const: 148 description:49 See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.50 51required:52 - compatible53 - reg54 - clocks55 - clock-names56 - '#clock-cells'57 - '#reset-cells'58 59additionalProperties: false60 61examples:62 - |63 #include <dt-bindings/clock/starfive,jh7110-crg.h>64 65 stgcrg: clock-controller@10230000 {66 compatible = "starfive,jh7110-stgcrg";67 reg = <0x10230000 0x10000>;68 clocks = <&osc>,69 <&syscrg JH7110_SYSCLK_HIFI4_CORE>,70 <&syscrg JH7110_SYSCLK_STG_AXIAHB>,71 <&syscrg JH7110_SYSCLK_USB_125M>,72 <&syscrg JH7110_SYSCLK_CPU_BUS>,73 <&syscrg JH7110_SYSCLK_HIFI4_AXI>,74 <&syscrg JH7110_SYSCLK_NOCSTG_BUS>,75 <&syscrg JH7110_SYSCLK_APB_BUS>;76 clock-names = "osc", "hifi4_core",77 "stg_axiahb", "usb_125m",78 "cpu_bus", "hifi4_axi",79 "nocstg_bus", "apb_bus";80 #clock-cells = <1>;81 #reset-cells = <1>;82 };83