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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/stericsson,u8500-clks.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: ST-Ericsson DB8500 (U8500) clocks8 9maintainers:10 - Ulf Hansson <ulf.hansson@linaro.org>11 - Linus Walleij <linus.walleij@linaro.org>12 13description: While named "U8500 clocks" these clocks are inside the14 DB8500 digital baseband system-on-chip and its siblings such as15 DB8520. These bindings consider the clocks present in the SoC16 itself, not off-chip clocks. There are four different on-chip17 clocks - RTC (32 kHz), CPU clock (SMP TWD), PRCMU (power reset and18 control management unit) clocks and PRCC (peripheral reset and19 clock controller) clocks. For some reason PRCC 4 does not exist so20 the itemization can be a bit unintuitive.21 22properties:23 compatible:24 enum:25 - stericsson,u8500-clks26 - stericsson,u8540-clks27 - stericsson,u9540-clks28 29 reg:30 items:31 - description: PRCC 1 register area32 - description: PRCC 2 register area33 - description: PRCC 3 register area34 - description: PRCC 5 register area35 - description: PRCC 6 register area36 37 prcmu-clock:38 description: A subnode with one clock cell for PRCMU (power, reset, control39 management unit) clocks. The cell indicates which PRCMU clock in the40 prcmu-clock node the consumer wants to use.41 type: object42 43 properties:44 '#clock-cells':45 const: 146 47 additionalProperties: false48 49 prcc-periph-clock:50 description: A subnode with two clock cells for PRCC (peripheral51 reset and clock controller) peripheral clocks. The first cell indicates52 which PRCC block the consumer wants to use, possible values are 1, 2, 3,53 5, 6. The second cell indicates which clock inside the PRCC block it54 wants, possible values are 0 thru 31.55 type: object56 57 properties:58 '#clock-cells':59 const: 260 61 additionalProperties: false62 63 prcc-kernel-clock:64 description: A subnode with two clock cells for PRCC (peripheral reset65 and clock controller) kernel clocks. The first cell indicates which PRCC66 block the consumer wants to use, possible values are 1, 2, 3, 5, 6. The67 second cell indicates which clock inside the PRCC block it wants, possible68 values are 0 thru 31.69 type: object70 71 properties:72 '#clock-cells':73 const: 274 75 additionalProperties: false76 77 prcc-reset-controller:78 description: A subnode with two reset cells for the reset portions of the79 PRCC (peripheral reset and clock controller). The first cell indicates80 which PRCC block the consumer wants to use, possible values are 1, 2, 381 5 and 6. The second cell indicates which reset line inside the PRCC block82 it wants to control, possible values are 0 thru 31.83 type: object84 85 properties:86 '#reset-cells':87 const: 288 89 additionalProperties: false90 91 rtc32k-clock:92 description: A subnode with zero clock cells for the 32kHz RTC clock.93 type: object94 95 properties:96 '#clock-cells':97 const: 098 99 additionalProperties: false100 101 smp-twd-clock:102 description: A subnode for the ARM SMP Timer Watchdog cluster with zero103 clock cells.104 type: object105 106 properties:107 '#clock-cells':108 const: 0109 110 additionalProperties: false111 112 clkout-clock:113 description: A subnode with three clock cells for externally routed clocks,114 output clocks. These are two PRCMU-internal clocks that can be divided and115 muxed out on the pads of the DB8500 SoC.116 type: object117 118 properties:119 '#clock-cells':120 description:121 The first cell indicates which output clock we are using,122 possible values are 0 (CLKOUT1) and 1 (CLKOUT2).123 The second cell indicates which clock we want to use as source,124 possible values are 0 thru 7, see the defines for the different125 source clocks.126 The third cell is a divider, legal values are 1 thru 63.127 const: 3128 129 additionalProperties: false130 131required:132 - compatible133 - reg134 - prcmu-clock135 - prcc-periph-clock136 - prcc-kernel-clock137 - rtc32k-clock138 - smp-twd-clock139 140additionalProperties: false141 142examples:143 - |144 #include <dt-bindings/clock/ste-db8500-clkout.h>145 clocks@8012 {146 compatible = "stericsson,u8500-clks";147 reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,148 <0x8000f000 0x1000>, <0xa03ff000 0x1000>,149 <0xa03cf000 0x1000>;150 151 prcmu_clk: prcmu-clock {152 #clock-cells = <1>;153 };154 155 prcc_pclk: prcc-periph-clock {156 #clock-cells = <2>;157 };158 159 prcc_kclk: prcc-kernel-clock {160 #clock-cells = <2>;161 };162 163 prcc_reset: prcc-reset-controller {164 #reset-cells = <2>;165 };166 167 rtc_clk: rtc32k-clock {168 #clock-cells = <0>;169 };170 171 smp_twd_clk: smp-twd-clock {172 #clock-cells = <0>;173 };174 175 clkout_clk: clkout-clock {176 #clock-cells = <3>;177 };178 };179