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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/ti,cdce925.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: TI CDCE913/925/937/949 programmable I2C clock synthesizers8 9maintainers:10 - Alexander Stein <alexander.stein@ew.tq-group.com>11 12description: |13 Flexible Low Power LVCMOS Clock Generator with SSC Support for EMI Reduction14 15 - CDCE(L)913: 1-PLL, 3 Outputs https://www.ti.com/product/cdce91316 - CDCE(L)925: 2-PLL, 5 Outputs https://www.ti.com/product/cdce92517 - CDCE(L)937: 3-PLL, 7 Outputs https://www.ti.com/product/cdce93718 - CDCE(L)949: 4-PLL, 9 Outputs https://www.ti.com/product/cdce94919 20properties:21 compatible:22 enum:23 - ti,cdce91324 - ti,cdce92525 - ti,cdce93726 - ti,cdce94927 28 reg:29 maxItems: 130 31 clocks:32 items:33 - description: fixed parent clock34 35 "#clock-cells":36 const: 137 38 vdd-supply:39 description: Regulator that provides 1.8V Vdd power supply40 41 vddout-supply:42 description: |43 Regulator that provides Vddout power supply.44 non-L variant: 2.5V or 3.3V for45 L variant: 1.8V for46 47 xtal-load-pf:48 $ref: /schemas/types.yaml#/definitions/uint3249 description: |50 Crystal load-capacitor value to fine-tune performance on a51 board, or to compensate for external influences.52 53patternProperties:54 "^PLL[1-4]$":55 type: object56 description: |57 optional child node can be used to specify spread58 spectrum clocking parameters for a board59 60 additionalProperties: false61 62 properties:63 spread-spectrum:64 $ref: /schemas/types.yaml#/definitions/uint3265 description: SSC mode as defined in the data sheet66 67 spread-spectrum-center:68 type: boolean69 description: |70 Use "centered" mode instead of "max" mode. When71 present, the clock runs at the requested frequency on average.72 Otherwise the requested frequency is the maximum value of the73 SCC range.74 75required:76 - compatible77 - reg78 - clocks79 - "#clock-cells"80 81additionalProperties: false82 83examples:84 - |85 i2c {86 #address-cells = <1>;87 #size-cells = <0>;88 89 cdce925: clock-controller@64 {90 compatible = "ti,cdce925";91 reg = <0x64>;92 clocks = <&xtal_27Mhz>;93 #clock-cells = <1>;94 xtal-load-pf = <5>;95 vdd-supply = <®_1v8>;96 vddout-supply = <®_3v3>;97 /* PLL options to get SSC 1% centered */98 PLL2 {99 spread-spectrum = <4>;100 spread-spectrum-center;101 };102 };103 };104