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1Binding for Texas Instruments DPLL clock.2 3This binding uses the common clock binding[1]. It assumes a4register-mapped DPLL with usually two selectable input clocks5(reference clock and bypass clock), with digital phase locked6loop logic for multiplying the input clock to a desired output7clock. This clock also typically supports different operation8modes (locked, low power stop etc.) This binding has several9sub-types, which effectively result in slightly different setup10for the actual DPLL clock.11 12[1] Documentation/devicetree/bindings/clock/clock-bindings.txt13 14Required properties:15- compatible : shall be one of:16 "ti,omap3-dpll-clock",17 "ti,omap3-dpll-core-clock",18 "ti,omap3-dpll-per-clock",19 "ti,omap3-dpll-per-j-type-clock",20 "ti,omap4-dpll-clock",21 "ti,omap4-dpll-x2-clock",22 "ti,omap4-dpll-core-clock",23 "ti,omap4-dpll-m4xen-clock",24 "ti,omap4-dpll-j-type-clock",25 "ti,omap5-mpu-dpll-clock",26 "ti,am3-dpll-no-gate-clock",27 "ti,am3-dpll-j-type-clock",28 "ti,am3-dpll-no-gate-j-type-clock",29 "ti,am3-dpll-clock",30 "ti,am3-dpll-core-clock",31 "ti,am3-dpll-x2-clock",32 "ti,omap2-dpll-core-clock",33 34- #clock-cells : from common clock binding; shall be set to 0.35- clocks : link phandles of parent clocks, first entry lists reference clock36 and second entry bypass clock37- reg : offsets for the register set for controlling the DPLL.38 Registers are listed in following order:39 "control" - contains the control register base address40 "idlest" - contains the idle status register base address41 "mult-div1" - contains the multiplier / divider register base address42 "autoidle" - contains the autoidle register base address (optional)43 "ssc-deltam" - DPLL supports spread spectrum clocking (SSC), contains44 the frequency spreading register base address (optional)45 "ssc-modfreq" - DPLL supports spread spectrum clocking (SSC), contains46 the modulation frequency register base address47 (optional)48 ti,am3-* dpll types do not have autoidle register49 ti,omap2-* dpll type does not support idlest / autoidle registers50 51Optional properties:52- DPLL mode setting - defining any one or more of the following overrides53 default setting.54 - ti,low-power-stop : DPLL supports low power stop mode, gating output55 - ti,low-power-bypass : DPLL output matches rate of parent bypass clock56 - ti,lock : DPLL locks in programmed rate57 - ti,min-div : the minimum divisor to start from to round the DPLL58 target rate59 - ti,ssc-deltam : DPLL supports spread spectrum clocking, frequency60 spreading in permille (10th of a percent)61 - ti,ssc-modfreq-hz : DPLL supports spread spectrum clocking, spread62 spectrum modulation frequency63 - ti,ssc-downspread : DPLL supports spread spectrum clocking, boolean64 to enable the downspread feature65 66Examples:67 dpll_core_ck: dpll_core_ck@44e00490 {68 #clock-cells = <0>;69 compatible = "ti,omap4-dpll-core-clock";70 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;71 reg = <0x490>, <0x45c>, <0x488>, <0x468>;72 };73 74 dpll2_ck: dpll2_ck@48004004 {75 #clock-cells = <0>;76 compatible = "ti,omap3-dpll-clock";77 clocks = <&sys_ck>, <&dpll2_fck>;78 ti,low-power-stop;79 ti,low-power-bypass;80 ti,lock;81 reg = <0x4>, <0x24>, <0x34>, <0x40>;82 };83 84 dpll_core_ck: dpll_core_ck@44e00490 {85 #clock-cells = <0>;86 compatible = "ti,am3-dpll-core-clock";87 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;88 reg = <0x90>, <0x5c>, <0x68>;89 };90 91 dpll_ck: dpll_ck {92 #clock-cells = <0>;93 compatible = "ti,omap2-dpll-core-clock";94 clocks = <&sys_ck>, <&sys_ck>;95 reg = <0x0500>, <0x0540>;96 };97 98 dpll_disp_ck: dpll_disp_ck {99 #clock-cells = <0>;100 compatible = "ti,am3-dpll-no-gate-clock";101 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;102 reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>;103 };104