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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Xilinx Versal clock controller8 9maintainers:10 - Michal Simek <michal.simek@amd.com>11 12description: |13 The clock controller is a hardware block of Xilinx versal clock tree. It14 reads required input clock frequencies from the devicetree and acts as clock15 provider for all clock consumers of PS clocks.16 17properties:18 compatible:19 oneOf:20 - enum:21 - xlnx,versal-clk22 - xlnx,zynqmp-clk23 - items:24 - enum:25 - xlnx,versal-net-clk26 - const: xlnx,versal-clk27 28 "#clock-cells":29 const: 130 31 clocks:32 description: List of clock specifiers which are external input33 clocks to the given clock controller.34 minItems: 235 maxItems: 836 37 clock-names:38 minItems: 239 maxItems: 840 41required:42 - compatible43 - "#clock-cells"44 - clocks45 - clock-names46 47additionalProperties: false48 49allOf:50 - if:51 properties:52 compatible:53 contains:54 enum:55 - xlnx,versal-clk56 57 then:58 properties:59 clocks:60 items:61 - description: reference clock62 - description: alternate reference clock for programmable logic63 64 clock-names:65 items:66 - const: ref67 - const: pl_alt_ref68 69 - if:70 properties:71 compatible:72 contains:73 enum:74 - xlnx,versal-net-clk75 76 then:77 properties:78 clocks:79 items:80 - description: reference clock81 - description: alternate reference clock for programmable logic82 - description: alternate reference clock83 84 clock-names:85 items:86 - const: ref87 - const: pl_alt_ref88 - const: alt_ref89 90 - if:91 properties:92 compatible:93 contains:94 enum:95 - xlnx,zynqmp-clk96 97 then:98 properties:99 clocks:100 minItems: 5101 items:102 - description: PS reference clock103 - description: reference clock for video system104 - description: alternative PS reference clock105 - description: auxiliary reference clock106 - description: transceiver reference clock107 - description: (E)MIO clock source (Optional clock)108 - description: GEM emio clock (Optional clock)109 - description: Watchdog external clock (Optional clock)110 111 clock-names:112 minItems: 5113 items:114 - const: pss_ref_clk115 - const: video_clk116 - const: pss_alt_ref_clk117 - const: aux_ref_clk118 - const: gt_crx_ref_clk119 - pattern: "^mio_clk[00-77]+.*$"120 - pattern: "gem[0-3]+_emio_clk.*$"121 - pattern: "swdt[0-1]+_ext_clk.*$"122 123examples:124 - |125 firmware {126 zynqmp_firmware: zynqmp-firmware {127 compatible = "xlnx,zynqmp-firmware";128 method = "smc";129 versal_clk: clock-controller {130 #clock-cells = <1>;131 compatible = "xlnx,versal-clk";132 clocks = <&ref>, <&pl_alt_ref>;133 clock-names = "ref", "pl_alt_ref";134 };135 };136 };137 138 clock-controller {139 #clock-cells = <1>;140 compatible = "xlnx,zynqmp-clk";141 clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,142 <&aux_ref_clk>, <>_crx_ref_clk>;143 clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk",144 "aux_ref_clk", "gt_crx_ref_clk";145 };146...147