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1Device Tree Clock bindings for the Zynq 7000 EPP2 3The Zynq EPP has several different clk providers, each with there own bindings.4The purpose of this document is to document their usage.5 6See clock_bindings.txt for more information on the generic clock bindings.7See Chapter 25 of Zynq TRM for more information about Zynq clocks.8 9== Clock Controller ==10The clock controller is a logical abstraction of Zynq's clock tree. It reads11required input clock frequencies from the devicetree and acts as clock provider12for all clock consumers of PS clocks.13 14Required properties:15 - #clock-cells : Must be 116 - compatible : "xlnx,ps7-clkc"17 - reg : SLCR offset and size taken via syscon < 0x100 0x100 >18 - ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ19 (usually 33 MHz oscillators are used for Zynq platforms)20 - clock-output-names : List of strings used to name the clock outputs. Shall be21 a list of the outputs given below.22 23Optional properties:24 - clocks : as described in the clock bindings25 - clock-names : as described in the clock bindings26 - fclk-enable : Bit mask to enable FCLKs statically at boot time.27 Bit [0..3] correspond to FCLK0..FCLK3. The corresponding28 FCLK will only be enabled if it is actually running at29 boot time.30 31Clock inputs:32The following strings are optional parameters to the 'clock-names' property in33order to provide an optional (E)MIO clock source.34 - swdt_ext_clk35 - gem0_emio_clk36 - gem1_emio_clk37 - mio_clk_XX # with XX = 00..5338...39 40Clock outputs:41 0: armpll42 1: ddrpll43 2: iopll44 3: cpu_6or4x45 4: cpu_3or2x46 5: cpu_2x47 6: cpu_1x48 7: ddr2x49 8: ddr3x50 9: dci51 10: lqspi52 11: smc53 12: pcap54 13: gem055 14: gem156 15: fclk057 16: fclk158 17: fclk259 18: fclk360 19: can061 20: can162 21: sdio063 22: sdio164 23: uart065 24: uart166 25: spi067 26: spi168 27: dma69 28: usb0_aper70 29: usb1_aper71 30: gem0_aper72 31: gem1_aper73 32: sdio0_aper74 33: sdio1_aper75 34: spi0_aper76 35: spi1_aper77 36: can0_aper78 37: can1_aper79 38: i2c0_aper80 39: i2c1_aper81 40: uart0_aper82 41: uart1_aper83 42: gpio_aper84 43: lqspi_aper85 44: smc_aper86 45: swdt87 46: dbg_trc88 47: dbg_apb89 90Example:91 clkc: clkc@100 {92 #clock-cells = <1>;93 compatible = "xlnx,ps7-clkc";94 ps-clk-frequency = <33333333>;95 reg = <0x100 0x100>;96 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",97 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",98 "dci", "lqspi", "smc", "pcap", "gem0", "gem1",99 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",100 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",101 "dma", "usb0_aper", "usb1_aper", "gem0_aper",102 "gem1_aper", "sdio0_aper", "sdio1_aper",103 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",104 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",105 "gpio_aper", "lqspi_aper", "smc_aper", "swdt",106 "dbg_trc", "dbg_apb";107 # optional props108 clocks = <&clkc 16>, <&clk_foo>;109 clock-names = "gem1_emio_clk", "can_mio_clk_23";110 };111