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1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Technologies, Inc. CPUFREQ8 9maintainers:10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>11 12description: |13 14 CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI)15 SoCs to manage frequency in hardware. It is capable of controlling frequency16 for multiple clusters.17 18properties:19 compatible:20 oneOf:21 - description: v1 of CPUFREQ HW22 items:23 - enum:24 - qcom,qcm2290-cpufreq-hw25 - qcom,sc7180-cpufreq-hw26 - qcom,sdm670-cpufreq-hw27 - qcom,sdm845-cpufreq-hw28 - qcom,sm6115-cpufreq-hw29 - qcom,sm6350-cpufreq-hw30 - qcom,sm8150-cpufreq-hw31 - const: qcom,cpufreq-hw32 33 - description: v2 of CPUFREQ HW (EPSS)34 items:35 - enum:36 - qcom,qdu1000-cpufreq-epss37 - qcom,sa8775p-cpufreq-epss38 - qcom,sc7280-cpufreq-epss39 - qcom,sc8280xp-cpufreq-epss40 - qcom,sdx75-cpufreq-epss41 - qcom,sm4450-cpufreq-epss42 - qcom,sm6375-cpufreq-epss43 - qcom,sm8250-cpufreq-epss44 - qcom,sm8350-cpufreq-epss45 - qcom,sm8450-cpufreq-epss46 - qcom,sm8550-cpufreq-epss47 - qcom,sm8650-cpufreq-epss48 - const: qcom,cpufreq-epss49 50 reg:51 minItems: 152 items:53 - description: Frequency domain 0 register region54 - description: Frequency domain 1 register region55 - description: Frequency domain 2 register region56 - description: Frequency domain 3 register region57 58 reg-names:59 minItems: 160 items:61 - const: freq-domain062 - const: freq-domain163 - const: freq-domain264 - const: freq-domain365 66 clocks:67 items:68 - description: XO Clock69 - description: GPLL0 Clock70 71 clock-names:72 items:73 - const: xo74 - const: alternate75 76 interrupts:77 minItems: 178 maxItems: 479 80 interrupt-names:81 minItems: 182 items:83 - const: dcvsh-irq-084 - const: dcvsh-irq-185 - const: dcvsh-irq-286 - const: dcvsh-irq-387 88 '#freq-domain-cells':89 const: 190 91 '#clock-cells':92 const: 193 94required:95 - compatible96 - reg97 - clocks98 - clock-names99 - '#freq-domain-cells'100 101additionalProperties: false102 103allOf:104 - if:105 properties:106 compatible:107 contains:108 enum:109 - qcom,qcm2290-cpufreq-hw110 then:111 properties:112 reg:113 minItems: 1114 maxItems: 1115 116 reg-names:117 minItems: 1118 maxItems: 1119 120 interrupts:121 minItems: 1122 maxItems: 1123 124 interrupt-names:125 minItems: 1126 127 - if:128 properties:129 compatible:130 contains:131 enum:132 - qcom,qdu1000-cpufreq-epss133 - qcom,sc7180-cpufreq-hw134 - qcom,sc8280xp-cpufreq-epss135 - qcom,sdm670-cpufreq-hw136 - qcom,sdm845-cpufreq-hw137 - qcom,sm4450-cpufreq-epss138 - qcom,sm6115-cpufreq-hw139 - qcom,sm6350-cpufreq-hw140 - qcom,sm6375-cpufreq-epss141 then:142 properties:143 reg:144 minItems: 2145 maxItems: 2146 147 reg-names:148 minItems: 2149 maxItems: 2150 151 interrupts:152 minItems: 2153 maxItems: 2154 155 interrupt-names:156 minItems: 2157 158 - if:159 properties:160 compatible:161 contains:162 enum:163 - qcom,sc7280-cpufreq-epss164 - qcom,sm8250-cpufreq-epss165 - qcom,sm8350-cpufreq-epss166 - qcom,sm8450-cpufreq-epss167 - qcom,sm8550-cpufreq-epss168 then:169 properties:170 reg:171 minItems: 3172 maxItems: 3173 174 reg-names:175 minItems: 3176 maxItems: 3177 178 interrupts:179 minItems: 3180 maxItems: 3181 182 interrupt-names:183 minItems: 3184 185 - if:186 properties:187 compatible:188 contains:189 enum:190 - qcom,sm8150-cpufreq-hw191 then:192 properties:193 reg:194 minItems: 3195 maxItems: 3196 197 reg-names:198 minItems: 3199 maxItems: 3200 201 # On some SoCs the Prime core shares the LMH irq with Big cores202 interrupts:203 minItems: 2204 maxItems: 2205 206 interrupt-names:207 minItems: 2208 209 210examples:211 - |212 #include <dt-bindings/clock/qcom,gcc-sdm845.h>213 #include <dt-bindings/clock/qcom,rpmh.h>214 215 // Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster216 // switch DCVS state together.217 cpus {218 #address-cells = <2>;219 #size-cells = <0>;220 221 CPU0: cpu@0 {222 device_type = "cpu";223 compatible = "qcom,kryo385";224 reg = <0x0 0x0>;225 enable-method = "psci";226 next-level-cache = <&L2_0>;227 qcom,freq-domain = <&cpufreq_hw 0>;228 clocks = <&cpufreq_hw 0>;229 L2_0: l2-cache {230 compatible = "cache";231 cache-unified;232 cache-level = <2>;233 next-level-cache = <&L3_0>;234 L3_0: l3-cache {235 compatible = "cache";236 cache-unified;237 cache-level = <3>;238 };239 };240 };241 242 CPU1: cpu@100 {243 device_type = "cpu";244 compatible = "qcom,kryo385";245 reg = <0x0 0x100>;246 enable-method = "psci";247 next-level-cache = <&L2_100>;248 qcom,freq-domain = <&cpufreq_hw 0>;249 clocks = <&cpufreq_hw 0>;250 L2_100: l2-cache {251 compatible = "cache";252 cache-unified;253 cache-level = <2>;254 next-level-cache = <&L3_0>;255 };256 };257 258 CPU2: cpu@200 {259 device_type = "cpu";260 compatible = "qcom,kryo385";261 reg = <0x0 0x200>;262 enable-method = "psci";263 next-level-cache = <&L2_200>;264 qcom,freq-domain = <&cpufreq_hw 0>;265 clocks = <&cpufreq_hw 0>;266 L2_200: l2-cache {267 compatible = "cache";268 cache-unified;269 cache-level = <2>;270 next-level-cache = <&L3_0>;271 };272 };273 274 CPU3: cpu@300 {275 device_type = "cpu";276 compatible = "qcom,kryo385";277 reg = <0x0 0x300>;278 enable-method = "psci";279 next-level-cache = <&L2_300>;280 qcom,freq-domain = <&cpufreq_hw 0>;281 clocks = <&cpufreq_hw 0>;282 L2_300: l2-cache {283 compatible = "cache";284 cache-unified;285 cache-level = <2>;286 next-level-cache = <&L3_0>;287 };288 };289 290 CPU4: cpu@400 {291 device_type = "cpu";292 compatible = "qcom,kryo385";293 reg = <0x0 0x400>;294 enable-method = "psci";295 next-level-cache = <&L2_400>;296 qcom,freq-domain = <&cpufreq_hw 1>;297 clocks = <&cpufreq_hw 1>;298 L2_400: l2-cache {299 compatible = "cache";300 cache-unified;301 cache-level = <2>;302 next-level-cache = <&L3_0>;303 };304 };305 306 CPU5: cpu@500 {307 device_type = "cpu";308 compatible = "qcom,kryo385";309 reg = <0x0 0x500>;310 enable-method = "psci";311 next-level-cache = <&L2_500>;312 qcom,freq-domain = <&cpufreq_hw 1>;313 clocks = <&cpufreq_hw 1>;314 L2_500: l2-cache {315 compatible = "cache";316 cache-unified;317 cache-level = <2>;318 next-level-cache = <&L3_0>;319 };320 };321 322 CPU6: cpu@600 {323 device_type = "cpu";324 compatible = "qcom,kryo385";325 reg = <0x0 0x600>;326 enable-method = "psci";327 next-level-cache = <&L2_600>;328 qcom,freq-domain = <&cpufreq_hw 1>;329 clocks = <&cpufreq_hw 1>;330 L2_600: l2-cache {331 compatible = "cache";332 cache-unified;333 cache-level = <2>;334 next-level-cache = <&L3_0>;335 };336 };337 338 CPU7: cpu@700 {339 device_type = "cpu";340 compatible = "qcom,kryo385";341 reg = <0x0 0x700>;342 enable-method = "psci";343 next-level-cache = <&L2_700>;344 qcom,freq-domain = <&cpufreq_hw 1>;345 clocks = <&cpufreq_hw 1>;346 L2_700: l2-cache {347 compatible = "cache";348 cache-unified;349 cache-level = <2>;350 next-level-cache = <&L3_0>;351 };352 };353 };354 355 soc {356 #address-cells = <1>;357 #size-cells = <1>;358 359 cpufreq@17d43000 {360 compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw";361 reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>;362 reg-names = "freq-domain0", "freq-domain1";363 364 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;365 clock-names = "xo", "alternate";366 367 #freq-domain-cells = <1>;368 #clock-cells = <1>;369 };370 };371...372