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1# SPDX-License-Identifier: GPL-2.02# Copyright (C) 2008-2011 Freescale Semiconductor Inc.3%YAML 1.24---5$id: http://devicetree.org/schemas/crypto/fsl,sec-v4.0.yaml#6$schema: http://devicetree.org/meta-schemas/core.yaml#7 8title: Freescale SEC 49 10maintainers:11 - '"Horia Geantă" <horia.geanta@nxp.com>'12 - Pankaj Gupta <pankaj.gupta@nxp.com>13 - Gaurav Jain <gaurav.jain@nxp.com>14 15description: |16 NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator17 Accelerator and Assurance Module (CAAM).18 19 SEC 4 h/w can process requests from 2 types of sources.20 1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4).21 2. Job Rings (HW interface between cores & SEC 4 registers).22 23 High Speed Data Path Configuration:24 25 HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts26 such as the P4080. The number of simultaneous dequeues the QI can make is27 equal to the number of Descriptor Controller (DECO) engines in a particular28 SEC version. E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus29 dequeue from 5 subportals simultaneously.30 31 Job Ring Data Path Configuration:32 33 Each JR is located on a separate 4k page, they may (or may not) be made visible34 in the memory partition devoted to a particular core. The P4080 has 4 JRs, so35 up to 4 JRs can be configured; and all 4 JRs process requests in parallel.36 37properties:38 compatible:39 oneOf:40 - items:41 - const: fsl,sec-v5.442 - const: fsl,sec-v5.043 - const: fsl,sec-v4.044 - items:45 - enum:46 - fsl,imx6ul-caam47 - fsl,sec-v5.048 - const: fsl,sec-v4.049 - const: fsl,sec-v4.050 51 reg:52 maxItems: 153 54 ranges:55 maxItems: 156 57 '#address-cells':58 enum: [1, 2]59 60 '#size-cells':61 enum: [1, 2]62 63 clocks:64 minItems: 165 maxItems: 466 67 clock-names:68 minItems: 169 maxItems: 470 items:71 enum: [mem, aclk, ipg, emi_slow]72 73 dma-coherent: true74 75 interrupts:76 maxItems: 177 78 fsl,sec-era:79 description: Defines the 'ERA' of the SEC device.80 $ref: /schemas/types.yaml#/definitions/uint3281 82patternProperties:83 '^jr@[0-9a-f]+$':84 type: object85 additionalProperties: false86 description:87 Job Ring (JR) Node. Defines data processing interface to SEC 4 across the88 peripheral bus for purposes of processing cryptographic descriptors. The89 specified address range can be made visible to one (or more) cores. The90 interrupt defined for this node is controlled within the address range of91 this node.92 93 properties:94 compatible:95 oneOf:96 - items:97 - const: fsl,sec-v5.4-job-ring98 - const: fsl,sec-v5.0-job-ring99 - const: fsl,sec-v4.0-job-ring100 - items:101 - const: fsl,sec-v5.0-job-ring102 - const: fsl,sec-v4.0-job-ring103 - const: fsl,sec-v4.0-job-ring104 105 reg:106 maxItems: 1107 108 interrupts:109 maxItems: 1110 111 fsl,liodn:112 description:113 Specifies the LIODN to be used in conjunction with the ppid-to-liodn114 table that specifies the PPID to LIODN mapping. Needed if the PAMU is115 used. Value is a 12 bit value where value is a LIODN ID for this JR.116 This property is normally set by boot firmware.117 $ref: /schemas/types.yaml#/definitions/uint32118 maximum: 0xfff119 120 '^rtic@[0-9a-f]+$':121 type: object122 additionalProperties: false123 description:124 Run Time Integrity Check (RTIC) Node. Defines a register space that125 contains up to 5 sets of addresses and their lengths (sizes) that will be126 checked at run time. After an initial hash result is calculated, these127 addresses are checked by HW to monitor any change. If any memory is128 modified, a Security Violation is triggered (see SNVS definition).129 130 properties:131 compatible:132 oneOf:133 - items:134 - const: fsl,sec-v5.4-rtic135 - const: fsl,sec-v5.0-rtic136 - const: fsl,sec-v4.0-rtic137 - const: fsl,sec-v4.0-rtic138 139 reg:140 items:141 - description: RTIC control and status register space.142 - description: RTIC recoverable error indication register space.143 minItems: 1144 145 ranges:146 maxItems: 1147 148 interrupts:149 maxItems: 1150 151 '#address-cells':152 const: 1153 154 '#size-cells':155 const: 1156 157 patternProperties:158 '^rtic-[a-z]@[0-9a-f]+$':159 type: object160 additionalProperties: false161 description:162 Run Time Integrity Check (RTIC) Memory Node defines individual RTIC163 memory regions that are used to perform run-time integrity check of164 memory areas that should not modified. The node defines a register165 that contains the memory address & length (combined) and a second166 register that contains the hash result in big endian format.167 168 properties:169 compatible:170 oneOf:171 - items:172 - const: fsl,sec-v5.4-rtic-memory173 - const: fsl,sec-v5.0-rtic-memory174 - const: fsl,sec-v4.0-rtic-memory175 - const: fsl,sec-v4.0-rtic-memory176 177 reg:178 items:179 - description: RTIC memory address180 - description: RTIC hash result181 182 fsl,liodn:183 description:184 Specifies the LIODN to be used in conjunction with the185 ppid-to-liodn table that specifies the PPID to LIODN mapping.186 Needed if the PAMU is used. Value is a 12 bit value where value187 is a LIODN ID for this JR. This property is normally set by boot188 firmware.189 $ref: /schemas/types.yaml#/definitions/uint32190 maximum: 0xfff191 192 fsl,rtic-region:193 description:194 Specifies the HW address (36 bit address) for this region195 followed by the length of the HW partition to be checked;196 the address is represented as a 64 bit quantity followed197 by a 32 bit length.198 $ref: /schemas/types.yaml#/definitions/uint32-array199 200required:201 - compatible202 - reg203 - ranges204 205additionalProperties: false206 207examples:208 - |209 crypto@300000 {210 compatible = "fsl,sec-v4.0";211 #address-cells = <1>;212 #size-cells = <1>;213 reg = <0x300000 0x10000>;214 ranges = <0 0x300000 0x10000>;215 interrupts = <92 2>;216 217 jr@1000 {218 compatible = "fsl,sec-v4.0-job-ring";219 reg = <0x1000 0x1000>;220 interrupts = <88 2>;221 };222 223 jr@2000 {224 compatible = "fsl,sec-v4.0-job-ring";225 reg = <0x2000 0x1000>;226 interrupts = <89 2>;227 };228 229 jr@3000 {230 compatible = "fsl,sec-v4.0-job-ring";231 reg = <0x3000 0x1000>;232 interrupts = <90 2>;233 };234 235 jr@4000 {236 compatible = "fsl,sec-v4.0-job-ring";237 reg = <0x4000 0x1000>;238 interrupts = <91 2>;239 };240 241 rtic@6000 {242 compatible = "fsl,sec-v4.0-rtic";243 #address-cells = <1>;244 #size-cells = <1>;245 reg = <0x6000 0x100>;246 ranges = <0x0 0x6100 0xe00>;247 248 rtic-a@0 {249 compatible = "fsl,sec-v4.0-rtic-memory";250 reg = <0x00 0x20>, <0x100 0x80>;251 };252 253 rtic-b@20 {254 compatible = "fsl,sec-v4.0-rtic-memory";255 reg = <0x20 0x20>, <0x200 0x80>;256 };257 258 rtic-c@40 {259 compatible = "fsl,sec-v4.0-rtic-memory";260 reg = <0x40 0x20>, <0x300 0x80>;261 };262 263 rtic-d@60 {264 compatible = "fsl,sec-v4.0-rtic-memory";265 reg = <0x60 0x20>, <0x500 0x80>;266 };267 };268 };269...270