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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/devfreq/nvidia,tegra30-actmon.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: NVIDIA Tegra30 Activity Monitor8 9maintainers:10 - Dmitry Osipenko <digetx@gmail.com>11 - Jon Hunter <jonathanh@nvidia.com>12 - Thierry Reding <thierry.reding@gmail.com>13 14description: |15 The activity monitor block collects statistics about the behaviour of other16 components in the system. This information can be used to derive the rate at17 which the external memory needs to be clocked in order to serve all requests18 from the monitored clients.19 20properties:21 compatible:22 enum:23 - nvidia,tegra30-actmon24 - nvidia,tegra114-actmon25 - nvidia,tegra124-actmon26 - nvidia,tegra210-actmon27 28 reg:29 maxItems: 130 31 clocks:32 maxItems: 233 34 clock-names:35 items:36 - const: actmon37 - const: emc38 39 resets:40 maxItems: 141 42 reset-names:43 items:44 - const: actmon45 46 interrupts:47 maxItems: 148 49 interconnects:50 minItems: 151 maxItems: 1252 53 interconnect-names:54 minItems: 155 maxItems: 1256 description:57 Should include name of the interconnect path for each interconnect58 entry. Consult TRM documentation for information about available59 memory clients, see MEMORY CONTROLLER and ACTIVITY MONITOR sections.60 61 operating-points-v2:62 description:63 Should contain freqs and voltages and opp-supported-hw property, which64 is a bitfield indicating SoC speedo ID mask.65 66 "#cooling-cells":67 const: 268 69required:70 - compatible71 - reg72 - clocks73 - clock-names74 - resets75 - reset-names76 - interrupts77 - interconnects78 - interconnect-names79 - operating-points-v280 - "#cooling-cells"81 82additionalProperties: false83 84examples:85 - |86 #include <dt-bindings/memory/tegra30-mc.h>87 88 mc: memory-controller@7000f000 {89 compatible = "nvidia,tegra30-mc";90 reg = <0x7000f000 0x400>;91 clocks = <&clk 32>;92 clock-names = "mc";93 94 interrupts = <0 77 4>;95 96 #iommu-cells = <1>;97 #reset-cells = <1>;98 #interconnect-cells = <1>;99 };100 101 emc: external-memory-controller@7000f400 {102 compatible = "nvidia,tegra30-emc";103 reg = <0x7000f400 0x400>;104 interrupts = <0 78 4>;105 clocks = <&clk 57>;106 107 nvidia,memory-controller = <&mc>;108 operating-points-v2 = <&dvfs_opp_table>;109 power-domains = <&domain>;110 111 #interconnect-cells = <0>;112 };113 114 actmon@6000c800 {115 compatible = "nvidia,tegra30-actmon";116 reg = <0x6000c800 0x400>;117 interrupts = <0 45 4>;118 clocks = <&clk 119>, <&clk 57>;119 clock-names = "actmon", "emc";120 resets = <&rst 119>;121 reset-names = "actmon";122 operating-points-v2 = <&dvfs_opp_table>;123 interconnects = <&mc TEGRA30_MC_MPCORER &emc>;124 interconnect-names = "cpu-read";125 #cooling-cells = <2>;126 };127